Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47302 )
Change subject: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's ......................................................................
soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's
Add a soc specific callback for getting the IIO IOAPIC enumeration ID.
Tested on ocp/deltalake.
Change-Id: Id504c2159066e6cddd01d30649921447bef17b12 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c 6 files changed, 47 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47302/1
diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index c70945a..46f9c5f 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -90,23 +90,19 @@ /* With XEON-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ #if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) const int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; - const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; #endif
#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) const int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 }; - const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; #endif /* Local APICs */ current = xeonsp_acpi_create_madt_lapics(current);
cur_index = 0; { - assert(cur_index < ARRAY_SIZE(ioapic_ids)); assert(cur_index < ARRAY_SIZE(gsi_bases)); - int ioapic_id = ioapic_ids[cur_index]; int gsi_base = gsi_bases[cur_index]; - current += add_madt_ioapic(current, 0, 0, ioapic_id, + current += add_madt_ioapic(current, 0, 0, PCH_IOAPIC_ID, hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase, gsi_base); ++cur_index; @@ -117,9 +113,8 @@ const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; if (ri->Personality != TYPE_UBOX_IIO) continue; - assert(cur_index < ARRAY_SIZE(ioapic_ids)); assert(cur_index < ARRAY_SIZE(gsi_bases)); - int ioapic_id = ioapic_ids[cur_index]; + int ioapic_id = soc_get_iio_ioapicid(socket, stack); int gsi_base = gsi_bases[cur_index]; uint32_t ioapic_base = ri->IoApicBase; /* diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 07c454e..2ebc9f1 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -12,7 +12,7 @@ };
void get_iiostack_info(struct iiostack_resource *info); - +uint8_t soc_get_iio_ioapicid(int socket, int stack); void xeonsp_init_cpu_config(void); const IIO_UDS *get_iio_uds(void); void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 9e7072e..c8f52f2 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -336,3 +336,24 @@ else return -1; } + +uint8_t soc_get_iio_ioapicid(int socket, int stack) +{ + uint8_t ioapic_id = socket ? 0xf : 0x9; + switch (stack) { + case CSTACK: + break; + case PSTACK0: + ioapic_id += 1; + break; + case PSTACK1: + ioapic_id += 2; + break; + case PSTACK2: + ioapic_id += 3; + break; + default: + return 0xff; + } + return ioapic_id; +} diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 6cb6828..f14064d 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -190,15 +190,6 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack, const IIO_UDS *hob) { - int IoApicID[] = { - // socket 0 - PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, - PC04_IOAPIC_ID, PC05_IOAPIC_ID, - // socket 1 - PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, - PC10_IOAPIC_ID, PC11_IOAPIC_ID, - }; - uint32_t enum_id; unsigned long tmp = current;
@@ -237,7 +228,7 @@ }
// Add IOAPIC entry - enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; + enum_id = soc_get_iio_ioapicid(socket, stack); printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 93481c9..ef48485 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -12,7 +12,7 @@ };
void get_iiostack_info(struct iiostack_resource *info); - +uint8_t soc_get_iio_ioapicid(int socket, int stack); void xeonsp_init_cpu_config(void); const IIO_UDS *get_iio_uds(void); void config_reset_cpl3_csrs(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index f9eddb2..97950d4 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -421,4 +421,25 @@ else return -1; } + +uint8_t soc_get_iio_ioapicid(int socket, int stack) +{ + uint8_t ioapic_id = socket ? 0xf : 0x9; + switch (stack) { + case CSTACK: + break; + case PSTACK0: + ioapic_id += 1; + break; + case PSTACK1: + ioapic_id += 2; + break; + case PSTACK2: + ioapic_id += 3; + break; + default: + return 0xff; + } + return ioapic_id; +} #endif
Hello build bot (Jenkins), Marc Jones, Jonathan Zhang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47302
to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's ......................................................................
soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's
Add a soc specific callback for getting the IIO IOAPIC enumeration ID.
Tested on ocp/deltalake.
Change-Id: Id504c2159066e6cddd01d30649921447bef17b12 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/soc_util.c 4 files changed, 45 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47302/2
Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47302 )
Change subject: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47302/1/src/soc/intel/xeon_sp/nb_ac... File src/soc/intel/xeon_sp/nb_acpi.c:
https://review.coreboot.org/c/coreboot/+/47302/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 200: }; Also remove the definitions in pci_devs.h
https://review.coreboot.org/c/coreboot/+/47302/2/src/soc/intel/xeon_sp/skx/s... File src/soc/intel/xeon_sp/skx/soc_util.c:
https://review.coreboot.org/c/coreboot/+/47302/2/src/soc/intel/xeon_sp/skx/s... PS2, Line 306: } I see that this matches the results of the ioapicid array, but what about the other skx Pstacks? Jonathan?
Hello build bot (Jenkins), Marc Jones, Jonathan Zhang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47302
to look at the new patch set (#3).
Change subject: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's ......................................................................
soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's
Add a soc specific callback for getting the IIO IOAPIC enumeration ID.
Tested on ocp/deltalake.
Change-Id: Id504c2159066e6cddd01d30649921447bef17b12 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/soc_util.c 6 files changed, 45 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47302/3
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47302 )
Change subject: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47302/1/src/soc/intel/xeon_sp/nb_ac... File src/soc/intel/xeon_sp/nb_acpi.c:
https://review.coreboot.org/c/coreboot/+/47302/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 200: };
Also remove the definitions in pci_devs. […]
Done
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47302 )
Change subject: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47302/2/src/soc/intel/xeon_sp/skx/s... File src/soc/intel/xeon_sp/skx/soc_util.c:
https://review.coreboot.org/c/coreboot/+/47302/2/src/soc/intel/xeon_sp/skx/s... PS2, Line 306: }
I see that this matches the results of the ioapicid array, but what about the other skx Pstacks? Jonathan?
From the looks of it PSTACK3 and PSTACK4 also feature IIO's on SKX. Looping up to PSTACK2 is also done elsewhere in the ACPI code so that might need fixing too?
Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47302 )
Change subject: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47302/2/src/soc/intel/xeon_sp/skx/s... File src/soc/intel/xeon_sp/skx/soc_util.c:
https://review.coreboot.org/c/coreboot/+/47302/2/src/soc/intel/xeon_sp/skx/s... PS2, Line 306: }
I see that this matches the results of the ioapicid array, but what about the other skx Pstacks? J […]
I don't know if PSTACK3/4 for MCP have IOAPICs. It seems that we need to check the stack personality from the HOB to program the IDs. Looping up to PSTACK2 may be valid.
Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47302 )
Change subject: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/47302/2/src/soc/intel/xeon_sp/skx/s... File src/soc/intel/xeon_sp/skx/soc_util.c:
https://review.coreboot.org/c/coreboot/+/47302/2/src/soc/intel/xeon_sp/skx/s... PS2, Line 306: }
I don't know if PSTACK3/4 for MCP have IOAPICs. […]
Looking at the hob display, I'm convinced that this is ok. I think it would be better to use the hob to check personalities instead of hard coding, but this is correct for these cpus.
Hello Marc Jones, build bot (Jenkins), Jonathan Zhang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47302
to look at the new patch set (#4).
Change subject: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's ......................................................................
soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's
Add a soc specific callback for getting the IIO IOAPIC enumeration ID.
Tested on ocp/deltalake.
Change-Id: Id504c2159066e6cddd01d30649921447bef17b12 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/soc_util.c 7 files changed, 46 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47302/4
Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47302 )
Change subject: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's ......................................................................
Patch Set 6: Code-Review+2
Hello Marc Jones, build bot (Jenkins), Jonathan Zhang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47302
to look at the new patch set (#7).
Change subject: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's ......................................................................
soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's
Add a soc specific callback for getting the IIO IOAPIC enumeration ID.
Tested on ocp/deltalake.
Change-Id: Id504c2159066e6cddd01d30649921447bef17b12 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/soc_util.c 7 files changed, 46 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47302/7
Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47302 )
Change subject: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's ......................................................................
Patch Set 7: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47302 )
Change subject: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's ......................................................................
soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's
Add a soc specific callback for getting the IIO IOAPIC enumeration ID.
Tested on ocp/deltalake.
Change-Id: Id504c2159066e6cddd01d30649921447bef17b12 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/47302 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Marc Jones marc@marcjonesconsulting.com --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/soc_util.c 7 files changed, 46 insertions(+), 40 deletions(-)
Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 3b4b713..fb4cd78 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -93,20 +93,17 @@ /* With XEON-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ #if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) const int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; - const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; #endif
#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) const int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 }; - const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; #endif /* Local APICs */ current = xeonsp_acpi_create_madt_lapics(current);
cur_index = 0; - ioapic_id = ioapic_ids[cur_index]; gsi_base = gsi_bases[cur_index]; - current += add_madt_ioapic(current, 0, 0, ioapic_id, + current += add_madt_ioapic(current, 0, 0, PCH_IOAPIC_ID, hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase, gsi_base); ++cur_index; @@ -117,9 +114,8 @@ &hob->PlatformData.IIO_resource[socket].StackRes[stack]; if (!is_iio_stack_res(ri)) continue; - assert(cur_index < ARRAY_SIZE(ioapic_ids)); assert(cur_index < ARRAY_SIZE(gsi_bases)); - ioapic_id = ioapic_ids[cur_index]; + ioapic_id = soc_get_iio_ioapicid(socket, stack); gsi_base = gsi_bases[cur_index]; uint32_t ioapic_base = ri->IoApicBase;
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 68dee28..33e257c 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -117,17 +117,5 @@
// ========== IOAPIC Definitions for DMAR/ACPI ======== #define PCH_IOAPIC_ID 0x08 -#define PC00_IOAPIC_ID 0x09 -#define PC01_IOAPIC_ID 0x0A -#define PC02_IOAPIC_ID 0x0B -#define PC03_IOAPIC_ID 0x0C -#define PC04_IOAPIC_ID 0x0D -#define PC05_IOAPIC_ID 0x0E -#define PC06_IOAPIC_ID 0x0F -#define PC07_IOAPIC_ID 0x10 -#define PC08_IOAPIC_ID 0x11 -#define PC09_IOAPIC_ID 0x12 -#define PC10_IOAPIC_ID 0x13 -#define PC11_IOAPIC_ID 0x14
#endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 578f67c..280bedc 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -63,3 +63,24 @@ else return -1; } + +uint8_t soc_get_iio_ioapicid(int socket, int stack) +{ + uint8_t ioapic_id = socket ? 0xf : 0x9; + switch (stack) { + case CSTACK: + break; + case PSTACK0: + ioapic_id += 1; + break; + case PSTACK1: + ioapic_id += 2; + break; + case PSTACK2: + ioapic_id += 3; + break; + default: + return 0xff; + } + return ioapic_id; +} diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index fc0dee7..2637017 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -16,6 +16,7 @@ unsigned int soc_get_num_cpus(void); void xeonsp_init_cpu_config(void); void set_bios_init_completion(void); +uint8_t soc_get_iio_ioapicid(int socket, int stack);
struct iiostack_resource { uint8_t no_of_stacks; diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 55c3d82..4a44980 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -184,15 +184,6 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack, const IIO_UDS *hob) { - int IoApicID[] = { - // socket 0 - PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, - PC04_IOAPIC_ID, PC05_IOAPIC_ID, - // socket 1 - PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, - PC10_IOAPIC_ID, PC11_IOAPIC_ID, - }; - uint32_t enum_id; unsigned long tmp = current;
@@ -231,7 +222,7 @@ }
// Add IOAPIC entry - enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; + enum_id = soc_get_iio_ioapicid(socket, stack); printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index b500c28..02df790 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -161,17 +161,5 @@
// ========== IOAPIC Definitions for DMAR/ACPI ======== #define PCH_IOAPIC_ID 0x08 -#define PC00_IOAPIC_ID 0x09 -#define PC01_IOAPIC_ID 0x0A -#define PC02_IOAPIC_ID 0x0B -#define PC03_IOAPIC_ID 0x0C -#define PC04_IOAPIC_ID 0x0D -#define PC05_IOAPIC_ID 0x0E -#define PC06_IOAPIC_ID 0x0F -#define PC07_IOAPIC_ID 0x10 -#define PC08_IOAPIC_ID 0x11 -#define PC09_IOAPIC_ID 0x12 -#define PC10_IOAPIC_ID 0x13 -#define PC11_IOAPIC_ID 0x14
#endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 7d95ae8..b903249 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -148,3 +148,24 @@ else return -1; } + +uint8_t soc_get_iio_ioapicid(int socket, int stack) +{ + uint8_t ioapic_id = socket ? 0xf : 0x9; + switch (stack) { + case CSTACK: + break; + case PSTACK0: + ioapic_id += 1; + break; + case PSTACK1: + ioapic_id += 2; + break; + case PSTACK2: + ioapic_id += 3; + break; + default: + return 0xff; + } + return ioapic_id; +}
-
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Marc Jones (Code Review)
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Patrick Georgi (Code Review)