Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69065 )
Change subject: /: Fix 16-bit read/write PCI_COMMAND register ......................................................................
/: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I6f5b64236cc9998e053e7c3ba5afc338d7367631 Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/drivers/siemens/nc_fpga/nc_fpga.c M src/drivers/usb/pci_ehci.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/xeon_sp/bootblock.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/intel/ibexpeak/early_pch.c 8 files changed, 23 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/69065/1
diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c index fe6eb15..e25e065 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga.c @@ -87,13 +87,13 @@ static void nc_fpga_init(struct device *dev) { void *bar0_ptr = NULL; - uint8_t cmd_reg; + uint16_t cmd_reg; uint32_t cap = 0;
/* All we need is mapped to BAR 0, get the address. */ bar0_ptr = (void *)(pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); - cmd_reg = pci_read_config8(dev, PCI_COMMAND); + cmd_reg = pci_read_config16(dev, PCI_COMMAND); /* Ensure BAR0 has a valid value. */ if (!bar0_ptr || !(cmd_reg & PCI_COMMAND_MEMORY)) return; diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 8e85426..f4e1d94 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -50,7 +50,7 @@
pci_s_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR);
- pci_s_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + pci_s_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
*base = CONFIG_EHCI_BAR; diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index c2c94ec..7a8c57a 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -982,7 +982,7 @@ { if (!disable_cse_idle(dev)) return DEV_IDLE; - pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
return DEV_ACTIVE; } @@ -991,7 +991,7 @@ { enable_cse_idle(dev);
- pci_and_config32(dev, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + pci_and_config16(dev, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); }
bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_state) diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 395a14d..de9abac 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -128,7 +128,7 @@ { pci_devfn_t pci_dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); pci_write_config32(pci_dev, PCI_BASE_ADDRESS_0, base); - pci_write_config32(pci_dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + pci_write_config16(pci_dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); }
@@ -173,7 +173,7 @@ static void gspi_set_base_addr(int devfn, struct device *dev, uintptr_t base) { pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); - pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); }
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index dd0b0ef..88e5496 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -18,10 +18,10 @@ printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
/* Enable SERR */ - pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
/* Enable Bus Master */ - pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Set Cache Line Size to 0x10 */ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE); diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 5ea09ac..48ff133 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -56,8 +56,8 @@ pch_enable_lpc();
/* Set up P2SB BAR. This is needed for PCR to work */ - uint8_t p2sb_cmd = pci_s_read_config8(PCH_DEV_P2SB, PCI_COMMAND); - pci_s_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY); + uint16_t p2sb_cmd = pci_s_read_config16(PCH_DEV_P2SB, PCI_COMMAND); + pci_s_write_config16(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY); pci_s_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); }
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 88e426a..46662ca 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -98,7 +98,7 @@ }
dev->command |= PCI_COMMAND_MASTER; - pci_write_config8(dev, PCI_COMMAND, dev->command); + pci_write_config16(dev, PCI_COMMAND, dev->command); printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); }
diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 4df47f3..b449386 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -50,7 +50,7 @@
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_BASE_ADDRESS_0, (uintptr_t)DEFAULT_HECIBAR); - pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, + pci_write_config16(PCI_DEV(0, 0x16, 0), PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); }
-
Elyes Haouas (Code Review)