Attention is currently required from: Jamie Ryu.
Hello Jamie Ryu,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/72695
to review the following change.
Change subject: mb/intel/mtlrvp: Enable CNVi BT Core and Wifi for mtlrvp ......................................................................
mb/intel/mtlrvp: Enable CNVi BT Core and Wifi for mtlrvp
This patch enables CNVi_BT Core and Wifi for mtlrvp based on mtlrvp schematics.
1. Enable CNVi BT Core in device tree 2. Enable CNVi Wifi (pci 14.3) device in device tree
BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump and able to boot mtlrvp (LP5/DDR5) to chromeOS. CNVi Mode = 1 Wi-Fi Core = 1 BT Core = 1 BT Audio Offload = 0 BT Interface = 1
Signed-off-by: Harsha B R harsha.b.r@intel.com Change-Id: I22575bf31b540f9dc1149a2766268285001b72f4 Signed-off-by: Jamie Ryu jamie.m.ryu@intel.com --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 39 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/72695/1
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 8cdbeea..15cdee1 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -36,6 +36,9 @@ register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)" register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)"
+ # Enable CNVi BT + register "cnvi_bt_core" = "true" + device domain 0 on device ref igpu on end device ref heci1 on end @@ -63,6 +66,15 @@ }" end # PCIE11 SSD Gen4 device ref xhci on end + + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref i2c0 on end device ref i2c1 on end device ref i2c2 on end