Patch set updated for coreboot: aa687ac mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.

[Edward O'Callaghan]

Edward O'Callaghan ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5355

-gerrit

commit aa687ac341408229e0a27f19f8266b28a291fdb1
Author: Edward O'Callaghan 
Date:   Sun Mar 9 17:46:39 2014 +1100

mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.

The platform dependent mainboard.c was incorrectly disabling the
    second clock signal feeding the GPP ports. This results in
    spurious hangs by calling the set_pcie_dereset() SB CIMx callback
    many times. This also stops coreboot from finding the second NIC
    behind the pci 15.0 bridge.

Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a
    Signed-off-by: Edward O'Callaghan 
---
 src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index b17bc6a..35c61fa 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -65,11 +65,11 @@ static void mainboard_enable(device_t dev)
    acpi_slp_type = acpi_get_sleep_type();
 #endif

-	/* enable GPP CLK0 thru CLK1 */
+	/* enable GPP CLK0 thru CLK3 (interleaved) */
    /* disable GPP CLK2 thru SLT_GFX_CLK */
    u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
    *(misc_mem_clk_cntrl + 0) = 0xFF;
-	*(misc_mem_clk_cntrl + 1) = 0x00;
+	*(misc_mem_clk_cntrl + 1) = 0xFF;
    *(misc_mem_clk_cntrl + 2) = 0x00;
    *(misc_mem_clk_cntrl + 3) = 0x00;
    *(misc_mem_clk_cntrl + 4) = 0x00;