Change in coreboot[master]: soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40842 )
Change subject: soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register ......................................................................
soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I23ca0c50b0b3c71710173b84d98c2e170ed3e45b Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/smihandler.c 2 files changed, 8 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40842/1
diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index b1f045a..7abf68c 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -515,24 +515,22 @@
void southcluster_enable_dev(struct device *dev) { - u32 reg32; + u16 reg16;
if (!dev->enabled) { printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); + reg16 = pci_read_config16(dev, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16);
/* Hide this device if possible */ pch_hide_devfn(dev->path.pci.devfn); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } }
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 276ab09..a3a53d2 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -50,7 +50,7 @@
for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16;
pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -60,9 +60,9 @@ continue;
/* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16);
/* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
Hello build bot (Jenkins), David Guckian, Vanessa Eusebio, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40842
to look at the new patch set (#2).
Change subject: soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register ......................................................................
soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I23ca0c50b0b3c71710173b84d98c2e170ed3e45b Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/smihandler.c 2 files changed, 9 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40842/2
David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40842 )
Change subject: soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register ......................................................................
Patch Set 2: Code-Review+1
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40842 )
Change subject: soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40842 )
Change subject: soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register ......................................................................
soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I23ca0c50b0b3c71710173b84d98c2e170ed3e45b Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/40842 Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: David Guckian Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/smihandler.c 2 files changed, 9 insertions(+), 11 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved David Guckian: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index d08405e..05c6484 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -514,24 +514,22 @@
void southcluster_enable_dev(struct device *dev) { - u32 reg32; + u16 reg16;
if (!dev->enabled) { printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16);
/* Hide this device if possible */ pch_hide_devfn(dev->path.pci.devfn); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } }
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 6b53964..b81eb11 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -49,7 +49,7 @@
for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16;
pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -59,9 +59,9 @@ continue;
/* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16);
/* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40842 )
Change subject: soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register ......................................................................
Patch Set 4:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4528 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4527 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4526 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4525
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
David Guckian (Code Review)
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HAOUAS Elyes (Code Review)
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Nico Huber (Code Review)
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Patrick Georgi (Code Review)