Change in coreboot[master]: soc/mediatek/mt8195: Disable UFS reference clock

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54011 )

Change subject: soc/mediatek/mt8195: Disable UFS reference clock
......................................................................

soc/mediatek/mt8195: Disable UFS reference clock

UFS reference clock (refclk) is enabled by default, which will cause
the UFSHCI to hold the SPM signal and lead to suspend failure. Since
UFS kernel driver is not built-in, disable refclk in coreboot stage.
Change UFSHCI base register to 0x11270000.

Signed-off-by: Yidi Lin 
Change-Id: I1386e59f802a9e3c938a7e8dbeea547fbcb02709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54011
Tested-by: build bot (Jenkins) 
Reviewed-by: Yu-Ping Wu 
---
M src/soc/mediatek/mt8195/Makefile.inc
M src/soc/mediatek/mt8195/include/soc/addressmap.h
M src/soc/mediatek/mt8195/soc.c
3 files changed, 4 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index 514acbd..ec6d78b 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -47,6 +47,7 @@
 ramstage-y += soc.c
 ramstage-y += ../common/timer.c timer.c
 ramstage-y += ../common/uart.c
+ramstage-y += ../common/ufs.c
 ramstage-y += ../common/usb.c usb.c
 ramstage-y += ../common/wdt.c
 ramstage-y += mt6360.c
diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h
index db24b77..60b730a 100644
--- a/src/soc/mediatek/mt8195/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h
@@ -61,6 +61,7 @@
    SPIS1_BASE		= IO_PHYS + 0x0101E000,
    SSUSB_IPPC_BASE		= IO_PHYS + 0x01203E00,
    MSDC0_BASE		= IO_PHYS + 0x01230000,
+	UFSHCI_BASE		= IO_PHYS + 0x01270000,
    SFLASH_REG_BASE		= IO_PHYS + 0x0132C000,
    EFUSEC_BASE		= IO_PHYS + 0x01C10000,
    MIPITX_BASE		= IO_PHYS + 0x01C80000,
@@ -73,7 +74,6 @@
    IOCFG_RB_BASE		= IO_PHYS + 0x01EB0000,
    IOCFG_TL_BASE		= IO_PHYS + 0x01F40000,
    MSDC0_TOP_BASE		= IO_PHYS + 0x01F50000,
-	UFSHCI_BASE		= IO_PHYS + 0x01FA0000,
    DISP_OVL0_BASE		= IO_PHYS + 0x0C000000,
    DISP_RDMA0_BASE		= IO_PHYS + 0x0C002000,
    DISP_COLOR0_BASE	= IO_PHYS + 0x0C003000,
diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c
index 4c98a66..cd161e8 100644
--- a/src/soc/mediatek/mt8195/soc.c
+++ b/src/soc/mediatek/mt8195/soc.c
@@ -3,6 +3,7 @@
 #include <device/device.h>
 #include <soc/emi.h>
 #include <soc/mmu_operations.h>
+#include <soc/ufs.h>
 #include <symbols.h>

static void soc_read_resources(struct device *dev)
@@ -13,6 +14,7 @@
 static void soc_init(struct device *dev)
 {
    mtk_mmu_disable_l2c_sram();
+	ufs_disable_refclk();
 }

static struct device_operations soc_ops = {