Change in coreboot[master]: soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE defines

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50205 )

Change subject: soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE defines
......................................................................

soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE defines

This define was copied over from Stoneyridge, but isn't present on
Picasso and newer.

Signed-off-by: Felix Held 
Change-Id: Ideb144c4bff441cf043a647b3f44a65691038eba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50205
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
---
M src/soc/amd/picasso/include/soc/southbridge.h
1 file changed, 0 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved

diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index f7edaad..d45c3b0 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -74,8 +74,6 @@
 #define   PM_LPC_AB_NO_BYPASS_EN	BIT(2)
 #define   PM_LPC_A20_EN			BIT(1)
 #define   PM_LPC_ENABLE			BIT(0)
-#define PM_USB_ENABLE			0xef
-#define   PM_USB_ALL_CONTROLLERS	0x7f

/* FCH MISC Registers 0xfed80e00 */
 #define GPP_CLK_CNTRL			0x00