[M] Change in coreboot[main]: soc/intel/xeon_sp/spr: Rewrite acpi_fill_cedt

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81274?usp=email )

Change subject: soc/intel/xeon_sp/spr: Rewrite acpi_fill_cedt
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Patch Set 5: Code-Review+1

(2 comments)

File src/soc/intel/xeon_sp/uncore_acpi.c:

https://review.coreboot.org/c/coreboot/+/81274/comment/8b656a26_e6b5c063 :
PS2, Line 599: 		/* FIXME: Use define for resource index */
> Is there a BAR on the CXL PCI device that can be used to read the MMIO instead of the FSP HOB? […]

One CXL device per stack is correct since CXL1.1/1.0 has a width of 16, a.k.a. to taking the full stack width. However, about CXL1.1/1.0 support on SPR, we are lack of device either and hence cannot be sure for other ways of resource access other than FSP.

https://review.coreboot.org/c/coreboot/+/81274/comment/d2bf1b92_d15e9df7 :
PS2, Line 612:
> I don't have any CXL cards.

Maybe we could just keep 1:1 refactoring against the originally logic in this patch and then merge it. For CXL test, we could leave to them who actually use it.