Arthur Heymans (arthur@aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17661
-gerrit
commit 024e86e5584bac3d5bcdf14f57ecd37efc387df2 Author: Arthur Heymans arthur@aheymans.xyz Date: Wed Nov 30 20:37:29 2016 +0100
nb/x4x: Move checkreset before SPD reading
It makes no sense to read SPDs if the system will reset anyway.
Change-Id: Id2ad9b04860b3e4939a149eef6b619a496179ff8 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- src/northbridge/intel/x4x/raminit.c | 43 +++++++++++++++++++++++++++++++ src/northbridge/intel/x4x/raminit_ddr2.c | 44 -------------------------------- 2 files changed, 43 insertions(+), 44 deletions(-)
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 122cab5..96d8a5a 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -316,6 +316,47 @@ static void sdram_detect_ram_speed(struct sysinfo *s) } }
+static void checkreset_ddr2(void) +{ + u8 pmcon2; + u8 reset = 0; + u32 pmir; + + pmir = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0xac); + pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + + if ((MCHBAR32(0xf14) & (1 << 8))) { + printk(BIOS_DEBUG, "Waiting for disks to timeout...\n"); + mdelay(2000); + reset = 1; + } + + if (pmcon2 & 0x80) { + pmcon2 &= ~0x80; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); + reset = 1; + + /* do magic 0xf0 thing. */ + u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); + pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); + reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); + pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); + } + if (reset) { + printk(BIOS_DEBUG, "Reset...\n"); + /* Do a global reset. only useful on ICH10 */ + pmir |= (1 << 20); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, pmir); + outb(0xe, 0xcf9); + asm ("hlt"); + } + pmir &= ~(1 << 20); + pmcon2 |= 0x80; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, pmir); + +} + /** * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 */ @@ -328,6 +369,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
pci_write_config8(PCI_DEV(0,0,0), 0xdf, 0xff);
+ checkreset_ddr2(); + memset(&s, 0, sizeof(struct sysinfo));
s.boot_path = boot_path; diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 09eea2a..cf6f1de 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -254,47 +254,6 @@ static void clkcross_ddr2(struct sysinfo *s) MCHBAR32(0x70c) = clkxtab[i][j][12]; }
-static void checkreset_ddr2(struct sysinfo *s) -{ - u8 pmcon2; - u8 reset = 0; - u32 pmir; - - pmir = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0xac); - pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - - if ((MCHBAR32(0xf14) & (1 << 8))) { - printk(BIOS_DEBUG, "Waiting for disks to timeout...\n"); - mdelay(2000); - reset = 1; - } - - if (pmcon2 & 0x80) { - pmcon2 &= ~0x80; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); - reset = 1; - - /* do magic 0xf0 thing. */ - u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); - } - if (reset) { - printk(BIOS_DEBUG, "Reset...\n"); - /* Do a global reset. only useful on ICH10 */ - pmir |= (1 << 20); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, pmir); - outb(0xe, 0xcf9); - asm ("hlt"); - } - pmir &= ~(1 << 20); - pmcon2 |= 0x80; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, pmir); - -} - static void setioclk_ddr2(struct sysinfo *s) { MCHBAR32(0x1bc) = 0x08060402; @@ -1872,9 +1831,6 @@ void raminit_ddr2(struct sysinfo *s) // Select timings based on SPD info sdram_detect_smallest_params2(s);
- // Reset if required - checkreset_ddr2(s); - // Clear self refresh MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x3;
-
Arthur Heymans