[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, TangYiwei, Tim Chu.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email )

Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes
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Patch Set 20:

(1 comment)

File src/soc/intel/xeon_sp/chip_gen6.c:

https://review.coreboot.org/c/coreboot/+/81316/comment/f1d68edc_1f12039c :
PS18, Line 145: 	soc_create_fsp24_domains(dp, upstream, sr, DOMAIN_TYPE_IOAT, pci_segment_group);
> Alternative would be: we split iio_domain_set_acpi_name between gen1 and gen6, for gen6, the 2nd cha […]

On gen1 there are multiple PCI domains of the same type on the same stack. It works on gen1. What's the problem here?

A good solution would be:
1. Add root UID into union xeon_domain_path on gen1
2. Use root UID to increment 2nd char of DOMAIN_TYPE
3. Update gen1 to use new root UID
4. Drop define DOMAIN_TYPE_UBX1, DOMAIN_TYPE_HQM1, DOMAIN_TYPE_CPM1
5. Use new iio_domain_set_acpi_name on gen6 as well