Change in coreboot[master]: soc/intel/icl: enable common CPU code

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45826 )

Change subject: soc/intel/icl: enable common CPU code
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soc/intel/icl: enable common CPU code

Enable CPU_INTEL_COMMON to make common CPU code available to CNL, which
gets used in CB:45535 and CB:45536 for CPPC entries generation.

Note: This also retrieves the VMX Kconfig and enables it by default,
like done for SKL and CNL already.

Since FSP always set the feature config lock, SET_IA32_FC_LOCK_BIT gets
selected statically by the SoC to reflect this in menuconfig.

Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb
Signed-off-by: Michael Niewöhner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45826
Reviewed-by: Angel Pons 
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/icelake/Kconfig
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 5736749..3b3d479 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -11,6 +11,8 @@
    select ARCH_ALL_STAGES_X86_32
    select BOOT_DEVICE_SUPPORTS_WRITES
    select CACHE_MRC_SETTINGS
+	select CPU_INTEL_COMMON
+	select SET_IA32_FC_LOCK_BIT
    select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
    select CPU_SUPPORTS_PM_TIMER_EMULATION
    select FSP_M_XIP