Change in ...coreboot[master]: soc/skl: Update SkipExtGfxScan in UPD from devtree

[Maxim Polyakov (Code Review)]

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32170

Change subject: soc/skl: Update SkipExtGfxScan in UPD from devtree
......................................................................

soc/skl: Update SkipExtGfxScan in UPD from devtree

The SkipExtGfxScan option is defined in the device tree, but doesn`t
update the value in the UPD. It uses the default value - 0. This
means that the FSP will scan all external graphics devices, in spite
of the configuration in devicetree.cb for a specific board.

Patch updates SkipExtGfxScan options in UPD from devicetree.cb.
This change affects all boards with skl/kbl processor.

Change-Id: Ie88a41bdf31f7c3e88df6c70c82a1cbf866372c4
Signed-off-by: Maxim Polyakov 
---
M src/soc/intel/skylake/romstage/romstage_fsp20.c
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32170/1

diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index b65c9ff..b0bf9bd 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -298,6 +298,7 @@

/* Set primary graphic device */
    soc_primary_gfx_config_params(m_cfg, config);
+	m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan;

mainboard_memory_init_params(mupd);
 }

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32170 )

Change subject: soc/skl: Update SkipExtGfxScan in UPD from devtree
......................................................................

Patch Set 1: Code-Review+2

Thanks for splitting this out. I don't expect any trouble
but if it would, further changes wouldn't affect the other
options :)

[Maxim Polyakov (Code Review)]

Hello Patrick Rudolph, Angel Pons, Youness Alaoui, Matt DeVillier, Duncan Laurie, Paul Menzel, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, caveh jalali, Gaggery Tsai, Nico Huber,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32170

to look at the new patch set (#2).

Change subject: soc/skl: Update SkipExtGfxScan in UPD from devtree
......................................................................

soc/skl: Update SkipExtGfxScan in UPD from devtree

The SkipExtGfxScan option is defined in the device tree, but doesn`t
update the value in the UPD. It uses the default value - 0. This
means that the FSP will scan all external graphics devices, in spite
of the configuration in devicetree.cb for a specific board.

Patch updates SkipExtGfxScan options in UPD from devicetree.cb.
This change affects all boards with skl/kbl processor.

Change-Id: Ie88a41bdf31f7c3e88df6c70c82a1cbf866372c4
Signed-off-by: Maxim Polyakov 
---
M src/soc/intel/skylake/romstage/romstage_fsp20.c
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32170/2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32170 )

Change subject: soc/skl: Update SkipExtGfxScan in UPD from devtree
......................................................................

soc/skl: Update SkipExtGfxScan in UPD from devtree

The SkipExtGfxScan option is defined in the device tree, but doesn`t
update the value in the UPD. It uses the default value - 0. This
means that the FSP will scan all external graphics devices, in spite
of the configuration in devicetree.cb for a specific board.

Patch updates SkipExtGfxScan options in UPD from devicetree.cb.
This change affects all boards with skl/kbl processor.

Change-Id: Ie88a41bdf31f7c3e88df6c70c82a1cbf866372c4
Signed-off-by: Maxim Polyakov 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32170
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/soc/intel/skylake/romstage/romstage_fsp20.c
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index d9b2706..dcfc363 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -354,6 +354,7 @@

/* Set primary graphic device */
    soc_primary_gfx_config_params(m_cfg, config);
+	m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan;

mainboard_memory_init_params(mupd);
 }