Change in coreboot[master]: nb/intel/sandybridge/pcie: Disable unused bridges

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19819 )

Change subject: nb/intel/sandybridge/pcie: Disable unused bridges
......................................................................

nb/intel/sandybridge/pcie: Disable unused bridges

Add a PCI Express Root Port driver.
Disable unused bridges that are not hot-plug capable.

Reduces idle power by ~1 Watt, as the PEG slot gets disabled.

Tested on Lenovo T430.

Change-Id: If67bafdea6a60986ecca2ecdb93c7f72359c4537
Signed-off-by: Patrick Rudolph 
---
M src/northbridge/intel/sandybridge/Makefile.inc
A src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/sandybridge/sandybridge.h
3 files changed, 82 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/19819/1

diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index a40fa15..88c4fb1 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -17,6 +17,7 @@

ramstage-y += ram_calc.c
 ramstage-y += northbridge.c
+ramstage-y += pcie.c
 ramstage-y += gma.c
 ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c
 ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c
diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c
new file mode 100644
index 0000000..98b5764
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/pcie.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Patrick Rudolph 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_ids.h>
+#include <southbridge/intel/common/pciehp.h>
+#include "sandybridge.h"
+
+static void pcie_scan_bridge(device_t dev)
+{
+	/* Normal PCIe Scan */
+	pciexp_scan_bridge(dev);
+
+	/* Hotplug capable ? */
+	if (pci_read_config32(dev, SLOTCAP) & (1 << 6))
+		return;
+
+	if (!dev_is_active_bridge(dev))
+		dev->ops->disable(dev);
+}
+
+static void pcie_disable(device_t dev)
+{
+	printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
+
+	dev->enabled = 0;
+}
+
+static void
+pcie_set_subsystem(device_t dev, unsigned int vendor, unsigned int device)
+{
+	/* NOTE: This is not the default position! */
+	if (!vendor || !device) {
+		pci_write_config32(dev, 0x94,
+				pci_read_config32(dev, 0));
+	} else {
+		pci_write_config32(dev, 0x94,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations pci_ops = {
+	.set_subsystem = pcie_set_subsystem,
+};
+
+static struct device_operations device_ops = {
+	.read_resources		= pci_bus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_bus_enable_resources,
+	.scan_bus		= pcie_scan_bridge,
+	.reset_bus		= pci_bus_reset,
+	.disable		= pcie_disable,
+	.ops_pci		= &pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = { 0x0101, 0x0105, 0x0109, 0x010d,
+						 0x0151, 0x0155, 0x0159, 0x015d,
+						 0 };
+
+static const struct pci_driver pch_pcie __pci_driver = {
+	.ops	 = &device_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
+	.devices = pci_device_ids,
+};
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index bc659be..8545d7f 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -109,7 +109,7 @@
 /* Device 0:1.0 PCI configuration space (PCI Express) */

#define BCTRL1		0x3e	/* 16bit */
-
+#define SLOTCAP		0xb4	/* Slot Capabilities Register */

/* Device 0:2.0 PCI configuration space (Graphics Device) */