Change in coreboot[master]: soc/intel/cannonlake: Merge soc_memory_init_params() into its caller

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52491 )

Change subject: soc/intel/cannonlake: Merge soc_memory_init_params() into its caller
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soc/intel/cannonlake: Merge soc_memory_init_params() into its caller

soc_memory_init_params() does not only configure memory init parameters.
Despite its name, it also configures many other things. Therefore, merge
it into its caller function platform_fsp_memory_init_params_cb() to
prevent confusions.

Built clevo/l140cu with BUILD_TIMELESS=1. coreboot.rom remains the same.

Change-Id: Id3b6395ea5d5cb714a412c856d66d4a9bcbd9c12
Signed-off-by: Felix Singer 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52491
Reviewed-by: Angel Pons 
Reviewed-by: Michael Niewöhner 
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/cannonlake/romstage/fsp_params.c
1 file changed, 5 insertions(+), 14 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, but someone else must approve
  Angel Pons: Looks good to me, approved
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 5eddf85..2bb3024 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -17,19 +17,21 @@

#include "../chip.h"

-static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config)
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
+	assert(dev != NULL);
+	const config_t *config = config_of(dev);
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
    FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig;
-
    unsigned int i;
    uint32_t mask = 0;
-	const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);

/*
     * Probe for no IGD and disable InternalGfx and panel power to prevent a
     * crash in FSP-M.
     */
+	dev = pcidev_path_on_root(SA_DEVFN_IGD);
    const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled;
    if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
    	/* Set IGD stolen size to 64MB. */
@@ -131,17 +133,6 @@
    if (config->DisableHeciRetry)
    	tconfig->DisableHeciRetry = config->DisableHeciRetry;
 #endif
-}
-
-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
-{
-	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
-	assert(dev != NULL);
-	const config_t *config = config_of(dev);
-	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
-	FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig;
-
-	soc_memory_init_params(mupd, config);

/* Enable SMBus controller based on config */
    dev = pcidev_path_on_root(PCH_DEVFN_SMBUS);