HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split ramint into desktop and mobile version ......................................................................
nb/i945: Split ramint into desktop and mobile version
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 68 insertions(+), 362 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/1
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index bae0589..34c9dce 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -23,7 +23,12 @@
romstage-y += romstage.c romstage-y += memmap.c -romstage-y += raminit.c +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC),y) +romstage-y += raminit_i945gc.c +else +romstage-y += raminit_i945gm.c +endif + romstage-y += early_init.c romstage-y += errata.c romstage-y += debug.c diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit_i945gc.c similarity index 90% copy from src/northbridge/intel/i945/raminit.c copy to src/northbridge/intel/i945/raminit_i945gc.c index 134d11f..d2adeba 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit_i945gc.c @@ -102,42 +102,28 @@
static int memclk(void) { - int offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; - - switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { + switch ((MCHBAR32(CLKCFG) >> 4) & 7) { case 1: return 400; case 2: return 533; case 3: return 667; default: printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, - ((MCHBAR32(CLKCFG) >> 4) & 7) - offset); + ((MCHBAR32(CLKCFG) >> 4) & 7)); } return -1; }
static u16 fsbclk(void) { - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 400; - case 1: return 533; - case 3: return 667; - default: - printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, - MCHBAR32(CLKCFG) & 7); - } - return 0xffff; - } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 1066; - case 1: return 533; - case 2: return 800; - default: - printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, - MCHBAR32(CLKCFG) & 7); - } - return 0xffff; + switch (MCHBAR32(CLKCFG) & 7) { + case 0: return 1066; + case 1: return 533; + case 2: return 800; + default: + printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, + MCHBAR32(CLKCFG) & 7); } + return 0xffff; }
static int sdram_capabilities_max_supported_memory_frequency(void) @@ -827,62 +813,6 @@ return nc; }
-#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) -/* Strength multiplier tables */ -static const u8 dual_channel_strength_multiplier[] = { - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22, - 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, - 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, - 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, - 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22, - 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, - 0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, - 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, - 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22 -}; - -static const u8 single_channel_strength_multiplier[] = { - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, - 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, - 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, - 0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, - 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, - 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 -}; -#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, @@ -936,7 +866,6 @@ 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00 }; -#endif
static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo) { @@ -1013,24 +942,13 @@ MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
/* We drive both channels with the same speed */ - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - switch (sysinfo->memory_frequency) { - case 400: - channeldll = 0x26262626; break; - case 533: - channeldll = 0x22222222; break; - case 667: - channeldll = 0x11111111; break; - } - } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - switch (sysinfo->memory_frequency) { - case 400: - channeldll = 0x33333333; break; - case 533: - channeldll = 0x24242424; break; - case 667: - channeldll = 0x25252525; break; - } + switch (sysinfo->memory_frequency) { + case 400: + channeldll = 0x33333333; break; + case 533: + channeldll = 0x24242424; break; + case 667: + channeldll = 0x25252525; break; }
for (i = 0; i < 4; i++) { @@ -1038,10 +956,8 @@ MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = channeldll; MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = channeldll; MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = channeldll; - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; - MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; - } + MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; + MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; } }
@@ -1754,7 +1670,6 @@ { u32 clkcfg; u8 reg8; - u8 offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0;
printk(BIOS_DEBUG, "Setting Memory Frequency... ");
@@ -1777,11 +1692,11 @@
switch (sysinfo->memory_frequency) { case 400: - clkcfg |= ((1 + offset) << 4); break; + clkcfg |= (1 << 4); break; case 533: - clkcfg |= ((2 + offset) << 4); break; + clkcfg |= (2 << 4); break; case 667: - clkcfg |= ((3 + offset) << 4); break; + clkcfg |= (3 << 4); break; default: die("Target Memory Frequency Error"); } @@ -1839,53 +1754,6 @@ /** * We add the indices according to our clocks from CLKCFG. */ -#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) - static const u32 data_clock_crossing[] = { - 0x00100401, 0x00000000, /* DDR400 FSB400 */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0x08040120, 0x00000000, /* DDR400 FSB533 */ - 0x00100401, 0x00000000, /* DDR533 FSB533 */ - 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */ - - 0x04020120, 0x00000010, /* DDR400 FSB667 */ - 0x10040280, 0x00000040, /* DDR533 FSB667 */ - 0x00100401, 0x00000000, /* DDR667 FSB667 */ - - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - }; - - static const u32 command_clock_crossing[] = { - 0x04020208, 0x00000000, /* DDR400 FSB400 */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0x00060108, 0x00000000, /* DDR400 FSB533 */ - 0x04020108, 0x00000000, /* DDR533 FSB533 */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0x00040318, 0x00000000, /* DDR400 FSB667 */ - 0x04020118, 0x00000000, /* DDR533 FSB667 */ - 0x02010804, 0x00000000, /* DDR667 FSB667 */ - - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - }; - -#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) - /* i945 G/P */ static const u32 data_clock_crossing[] = { 0xffffffff, 0xffffffff, /* nonexistent */ 0xffffffff, 0xffffffff, /* nonexistent */ @@ -1929,7 +1797,6 @@ 0x02010804, 0x00000000, /* DDR533 FSB1066 */ 0x180601c0, 0x00000020, /* DDR667 FSB1066 */ }; -#endif
printk(BIOS_DEBUG, "Programming Clock Crossing...");
@@ -2156,21 +2023,6 @@ reg32 |= (1 << 12) | (1 << 11); MCHBAR32(C1DRC1) = reg32;
- if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - if (i945_silicon_revision() > 1) { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); - - MCHBAR16(UPMC1) = 0x1010 | peg_bits; - } else { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); - - /* Rev 0 and 1 */ - MCHBAR16(UPMC1) = 0x0010 | peg_bits; - } - } - reg16 = MCHBAR16(UPMC2); reg16 &= 0xfc00; reg16 |= 0x0100; @@ -2474,22 +2326,17 @@ { u8 clocks[2] = { 0, 0 };
-#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) -#define CLOCKS_WIDTH 2 -#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) -#define CLOCKS_WIDTH 3 -#endif if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) - clocks[0] |= (1 << CLOCKS_WIDTH)-1; + clocks[0] |= (1 << 3) - 1;
if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) - clocks[0] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; + clocks[0] |= ((1 << 3) - 1) << 3;
if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) - clocks[1] |= (1 << CLOCKS_WIDTH)-1; + clocks[1] |= (1 << 3) - 1;
if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) - clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; + clocks[1] |= ((1 << 3) - 1) << 3;
#if CONFIG(OVERRIDE_CLOCK_DISABLE) /* Usually system firmware turns off system memory clock signals @@ -2726,10 +2573,7 @@ * Program Graphics Frequency * Set core display and render clock on 945GC to the max */ - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) - sdram_program_graphics_frequency(&sysinfo); - else - pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534); + pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534);
/* Program System Memory Frequency */ sdram_program_memory_frequency(&sysinfo); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit_i945gm.c similarity index 90% rename from src/northbridge/intel/i945/raminit.c rename to src/northbridge/intel/i945/raminit_i945gm.c index 134d11f..74c5bbc 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit_i945gm.c @@ -102,42 +102,28 @@
static int memclk(void) { - int offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; - - switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { + switch (((MCHBAR32(CLKCFG) >> 4) & 7) - 1) { case 1: return 400; case 2: return 533; case 3: return 667; default: printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, - ((MCHBAR32(CLKCFG) >> 4) & 7) - offset); + ((MCHBAR32(CLKCFG) >> 4) & 7) - 1); } return -1; }
static u16 fsbclk(void) { - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 400; - case 1: return 533; - case 3: return 667; - default: - printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, - MCHBAR32(CLKCFG) & 7); - } - return 0xffff; - } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 1066; - case 1: return 533; - case 2: return 800; - default: - printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, - MCHBAR32(CLKCFG) & 7); - } - return 0xffff; + switch (MCHBAR32(CLKCFG) & 7) { + case 0: return 400; + case 1: return 533; + case 3: return 667; + default: + printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, + MCHBAR32(CLKCFG) & 7); } + return 0xffff; }
static int sdram_capabilities_max_supported_memory_frequency(void) @@ -827,7 +813,6 @@ return nc; }
-#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) /* Strength multiplier tables */ static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, @@ -882,61 +867,6 @@ 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 }; -#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) -static const u8 dual_channel_strength_multiplier[] = { - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33 -}; - -static const u8 single_channel_strength_multiplier[] = { - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00 -}; -#endif
static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo) { @@ -1013,24 +943,13 @@ MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
/* We drive both channels with the same speed */ - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - switch (sysinfo->memory_frequency) { - case 400: - channeldll = 0x26262626; break; - case 533: - channeldll = 0x22222222; break; - case 667: - channeldll = 0x11111111; break; - } - } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - switch (sysinfo->memory_frequency) { - case 400: - channeldll = 0x33333333; break; - case 533: - channeldll = 0x24242424; break; - case 667: - channeldll = 0x25252525; break; - } + switch (sysinfo->memory_frequency) { + case 400: + channeldll = 0x26262626; break; + case 533: + channeldll = 0x22222222; break; + case 667: + channeldll = 0x11111111; break; }
for (i = 0; i < 4; i++) { @@ -1038,10 +957,6 @@ MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = channeldll; MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = channeldll; MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = channeldll; - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; - MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; - } } }
@@ -1754,8 +1669,7 @@ { u32 clkcfg; u8 reg8; - u8 offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; - + printk(BIOS_DEBUG, "Setting Memory Frequency... ");
clkcfg = MCHBAR32(CLKCFG); @@ -1777,11 +1691,11 @@
switch (sysinfo->memory_frequency) { case 400: - clkcfg |= ((1 + offset) << 4); break; + clkcfg |= (2 << 4); break; case 533: - clkcfg |= ((2 + offset) << 4); break; + clkcfg |= (3 << 4); break; case 667: - clkcfg |= ((3 + offset) << 4); break; + clkcfg |= (4 << 4); break; default: die("Target Memory Frequency Error"); } @@ -1839,7 +1753,6 @@ /** * We add the indices according to our clocks from CLKCFG. */ -#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) static const u32 data_clock_crossing[] = { 0x00100401, 0x00000000, /* DDR400 FSB400 */ 0xffffffff, 0xffffffff, /* nonexistent */ @@ -1884,52 +1797,6 @@ 0xffffffff, 0xffffffff, /* nonexistent */ };
-#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) - /* i945 G/P */ - static const u32 data_clock_crossing[] = { - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0x10080201, 0x00000000, /* DDR400 FSB533 */ - 0x00100401, 0x00000000, /* DDR533 FSB533 */ - 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */ - - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0x04020108, 0x00000000, /* DDR400 FSB800 */ - 0x00020108, 0x00000000, /* DDR533 FSB800 */ - 0x00080201, 0x00000000, /* DDR667 FSB800 */ - - 0x00010402, 0x00000000, /* DDR400 FSB1066 */ - 0x04020108, 0x00000000, /* DDR533 FSB1066 */ - 0x08040110, 0x00000000, /* DDR667 FSB1066 */ - }; - - static const u32 command_clock_crossing[] = { - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0x00010800, 0x00000402, /* DDR400 FSB533 */ - 0x01000400, 0x00000200, /* DDR533 FSB533 */ - 0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */ - - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0x02010804, 0x00000000, /* DDR400 FSB800 */ - 0x00010402, 0x00000000, /* DDR533 FSB800 */ - 0x04020130, 0x00000008, /* DDR667 FSB800 */ - - 0x00020904, 0x00000000, /* DDR400 FSB1066 */ - 0x02010804, 0x00000000, /* DDR533 FSB1066 */ - 0x180601c0, 0x00000020, /* DDR667 FSB1066 */ - }; -#endif
printk(BIOS_DEBUG, "Programming Clock Crossing...");
@@ -2156,19 +2023,17 @@ reg32 |= (1 << 12) | (1 << 11); MCHBAR32(C1DRC1) = reg32;
- if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - if (i945_silicon_revision() > 1) { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); + if (i945_silicon_revision() > 1) { + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = (1 << 5) | (1 << 0);
- MCHBAR16(UPMC1) = 0x1010 | peg_bits; - } else { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); + MCHBAR16(UPMC1) = 0x1010 | peg_bits; + } else { + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = (1 << 5) | (1 << 0);
- /* Rev 0 and 1 */ - MCHBAR16(UPMC1) = 0x0010 | peg_bits; - } + /* Rev 0 and 1 */ + MCHBAR16(UPMC1) = 0x0010 | peg_bits; }
reg16 = MCHBAR16(UPMC2); @@ -2474,22 +2339,17 @@ { u8 clocks[2] = { 0, 0 };
-#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) -#define CLOCKS_WIDTH 2 -#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) -#define CLOCKS_WIDTH 3 -#endif if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) - clocks[0] |= (1 << CLOCKS_WIDTH)-1; + clocks[0] |= (1 << 2) - 1;
if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) - clocks[0] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; + clocks[0] |= ((1 << 2) - 1) << 2;
if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) - clocks[1] |= (1 << CLOCKS_WIDTH)-1; + clocks[1] |= (1 << 2) - 1;
if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) - clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; + clocks[1] |= ((1 << 2)-1) << 2;
#if CONFIG(OVERRIDE_CLOCK_DISABLE) /* Usually system firmware turns off system memory clock signals @@ -2726,10 +2586,7 @@ * Program Graphics Frequency * Set core display and render clock on 945GC to the max */ - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) - sdram_program_graphics_frequency(&sysinfo); - else - pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534); + sdram_program_graphics_frequency(&sysinfo);
/* Program System Memory Frequency */ sdram_program_memory_frequency(&sysinfo);
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split ramint into desktop and mobile version ......................................................................
Patch Set 1:
(8 comments)
https://review.coreboot.org/c/coreboot/+/39821/1/src/northbridge/intel/i945/... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/1/src/northbridge/intel/i945/... PS1, Line 436: die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n"); line over 96 characters
https://review.coreboot.org/c/coreboot/+/39821/1/src/northbridge/intel/i945/... PS1, Line 904: if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) line over 96 characters
https://review.coreboot.org/c/coreboot/+/39821/1/src/northbridge/intel/i945/... PS1, Line 1363: case 533: break; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/39821/1/src/northbridge/intel/i945/... PS1, Line 1364: case 667: tRD_min += 1; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/39821/1/src/northbridge/intel/i945/... PS1, Line 1366: case 800: tRD_min += 2; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/39821/1/src/northbridge/intel/i945/... PS1, Line 1368: case 1066: tRD_min += 3; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/39821/1/src/northbridge/intel/i945/... PS1, Line 2391: printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero); line over 96 characters
https://review.coreboot.org/c/coreboot/+/39821/1/src/northbridge/intel/i945/... File src/northbridge/intel/i945/raminit_i945gm.c:
https://review.coreboot.org/c/coreboot/+/39821/1/src/northbridge/intel/i945/... PS1, Line 1672: trailing whitespace
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: nb/i945: Split ramint into desktop and mobile version ......................................................................
nb/i945: Split ramint into desktop and mobile version
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 67 insertions(+), 361 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split ramint into desktop and mobile version ......................................................................
Patch Set 2:
(7 comments)
https://review.coreboot.org/c/coreboot/+/39821/2/src/northbridge/intel/i945/... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/2/src/northbridge/intel/i945/... PS2, Line 436: die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n"); line over 96 characters
https://review.coreboot.org/c/coreboot/+/39821/2/src/northbridge/intel/i945/... PS2, Line 904: if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) line over 96 characters
https://review.coreboot.org/c/coreboot/+/39821/2/src/northbridge/intel/i945/... PS2, Line 1363: case 533: break; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/39821/2/src/northbridge/intel/i945/... PS2, Line 1364: case 667: tRD_min += 1; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/39821/2/src/northbridge/intel/i945/... PS2, Line 1366: case 800: tRD_min += 2; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/39821/2/src/northbridge/intel/i945/... PS2, Line 1368: case 1066: tRD_min += 3; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/39821/2/src/northbridge/intel/i945/... PS2, Line 2391: printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero); line over 96 characters
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: nb/i945: Split ramint into desktop and mobile version ......................................................................
nb/i945: Split ramint into desktop and mobile version
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 78 insertions(+), 495 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split ramint into desktop and mobile version ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/3/src/northbridge/intel/i945/... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/3/src/northbridge/intel/i945/... PS3, Line 2268: printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero); line over 96 characters
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#4).
Change subject: nb/i945: Split ramint into desktop and mobile version ......................................................................
nb/i945: Split ramint into desktop and mobile version
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 80 insertions(+), 525 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/4
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#5).
Change subject: nb/i945: Split ramint into desktop and mobile version ......................................................................
nb/i945: Split ramint into desktop and mobile version
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 84 insertions(+), 532 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/5
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#6).
Change subject: nb/i945: Split ramint into desktop and mobile version ......................................................................
nb/i945: Split ramint into desktop and mobile version
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 99 insertions(+), 537 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/6
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split ramint into desktop and mobile version ......................................................................
Patch Set 6:
(4 comments)
It would be nice if this could be split up a bit. The idea is that cosmetic changes should result in a reprodible coreboot.rom (identical before and after applying this change) when using BUILD_TIMELESS=1
If the binary does not change, it's not going to break anything 😄
https://review.coreboot.org/c/coreboot/+/39821/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39821/6//COMMIT_MSG@7 PS6, Line 7: ramint raminit
https://review.coreboot.org/c/coreboot/+/39821/6/src/northbridge/intel/i945/... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/6/src/northbridge/intel/i945/... PS6, Line 450: by this chipset Avoid changing this here, as it breaks BUILD_TIMELESS=1 verifiability.
https://review.coreboot.org/c/coreboot/+/39821/6/src/northbridge/intel/i945/... PS6, Line 285: i945 not all i945 though
https://review.coreboot.org/c/coreboot/+/39821/6/src/northbridge/intel/i945/... PS6, Line 873: if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && Can we split the cosmetic changes into a separate change?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split ramint into desktop and mobile version ......................................................................
Patch Set 6:
I would suggest splitting this up in various patches:
- do a cosmetic cleanup of the affected files - duplicate the file for each chipset - remove dead code on i945gm - remove dead code on i945gc
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split ramint into desktop and mobile version ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39821/6//COMMIT_MSG@8 PS6, Line 8: Please elaborate in the commit message, why the split is necessary.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#7).
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
nb/i945: Split raminit into desktop and mobile version
Split up ramint.c to make maintenance easier.
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 99 insertions(+), 537 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/7
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39821/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39821/6//COMMIT_MSG@7 PS6, Line 7: ramint
raminit
Done
https://review.coreboot.org/c/coreboot/+/39821/6//COMMIT_MSG@8 PS6, Line 8:
Please elaborate in the commit message, why the split is necessary.
Done
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/6/src/northbridge/intel/i945/... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/6/src/northbridge/intel/i945/... PS6, Line 285: i945
not all i945 though
I think all of them. I've tested the intel's ROM for d945gclf (supposed to have only 2 DIMMs), on my desktop with 4 DIMMs and it recongnises all of the 4 DIMMs
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/6/src/northbridge/intel/i945/... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/6/src/northbridge/intel/i945/... PS6, Line 285: i945
I think all of them. […]
I meant that i945gm does not support four DIMMs...
In any case, testing with another i945gc board that only has two DIMMs would be nice after the actual fixes are done.
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/6/src/northbridge/intel/i945/... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/6/src/northbridge/intel/i945/... PS6, Line 285: i945
I meant that i945gm does not support four DIMMs... […]
here is the file for 945gc. understood, I'll change it to "i945 desktop version".
it would be nice if some one can test - on already supported board ... - on not yet supported board 😊 (maybe dell 😄 )
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#8).
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
nb/i945: Split raminit into desktop and mobile version
Split up ramint.c to make maintenance easier.
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 99 insertions(+), 537 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/8
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39821/8//COMMIT_MSG@9 PS8, Line 9: Split up ramint.c to make maintenance easier. Reference the datasheet, and mention what parts differ mainly to justify a split?
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39821/8//COMMIT_MSG@9 PS8, Line 9: Split up ramint.c to make maintenance easier.
Reference the datasheet, and mention what parts differ mainly to justify a split?
There is no datasheet even in the public datasheet for mobile version, there many undocumented registers. the difference between desktop and mobile version is : the 1st one is selected with NORTHBRIDGE_INTEL_SUBTYPE_I945GC and the 2nd with NORTHBRIDGE_INTEL_SUBTYPE_I945GM
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39821/6/src/northbridge/intel/i945/... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/6/src/northbridge/intel/i945/... PS6, Line 450: by this chipset
Avoid changing this here, as it breaks BUILD_TIMELESS=1 verifiability.
Done
https://review.coreboot.org/c/coreboot/+/39821/6/src/northbridge/intel/i945/... PS6, Line 285: i945
here is the file for 945gc. […]
Done
https://review.coreboot.org/c/coreboot/+/39821/6/src/northbridge/intel/i945/... PS6, Line 873: if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) &&
Can we split the cosmetic changes into a separate change?
Done
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#9).
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
nb/i945: Split raminit into desktop and mobile version
Split up ramint.c to make maintenance easier.
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 98 insertions(+), 541 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/9
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39821/9//COMMIT_MSG@9 PS9, Line 9: ramint ramin*i*t
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39821/9//COMMIT_MSG@9 PS9, Line 9: ramint
ramin*i*t
Done
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#10).
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
nb/i945: Split raminit into desktop and mobile version
Split up raminit.c to make maintenance easier.
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 98 insertions(+), 541 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/10
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#12).
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
nb/i945: Split raminit into desktop and mobile version
Split up raminit.c to make maintenance easier.
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 148 insertions(+), 583 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/12
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#13).
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
nb/i945: Split raminit into desktop and mobile version
Split up raminit.c to make maintenance easier.
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 103 insertions(+), 565 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/13
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#14).
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
nb/i945: Split raminit into desktop and mobile version
Split up raminit.c to make maintenance easier.
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 82 insertions(+), 542 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/14
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/14/src/northbridge/intel/i945... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/14/src/northbridge/intel/i945... PS14, Line 408: printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32); line over 96 characters
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#15).
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
nb/i945: Split raminit into desktop and mobile version
Split up raminit.c to make maintenance easier.
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 91 insertions(+), 554 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/15
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/15/src/northbridge/intel/i945... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/15/src/northbridge/intel/i945... PS15, Line 407: printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32); line over 96 characters
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#16).
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
nb/i945: Split raminit into desktop and mobile version
Split up raminit.c to make maintenance easier.
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 97 insertions(+), 560 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/16
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/16/src/northbridge/intel/i945... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/16/src/northbridge/intel/i945... PS16, Line 407: printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32); line over 96 characters
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 16:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39821/16/src/northbridge/intel/i945... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/16/src/northbridge/intel/i945... PS16, Line 913: MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; Don't move this write
https://review.coreboot.org/c/coreboot/+/39821/16/src/northbridge/intel/i945... PS16, Line 2149: if ((sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED && Don't change this here please. It breaks verification...
https://review.coreboot.org/c/coreboot/+/39821/16/src/northbridge/intel/i945... PS16, Line 2198: if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) Why did the CLOCKS_WIDTH macro disappear?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 16: Code-Review+1
+1 because i945gm remains unchanged. If you make i945gc remain unchanged as well, I'll give a +2 😄
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#17).
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
nb/i945: Split raminit into desktop and mobile version
Split up raminit.c to make maintenance easier.
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 86 insertions(+), 557 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/17
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/17/src/northbridge/intel/i945... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/17/src/northbridge/intel/i945... PS17, Line 407: printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32); line over 96 characters
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#18).
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
nb/i945: Split raminit into desktop and mobile version
Split up raminit.c to make maintenance easier.
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 85 insertions(+), 556 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/18
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 18:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/18/src/northbridge/intel/i945... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/18/src/northbridge/intel/i945... PS18, Line 407: printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32); line over 96 characters
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 18:
(3 comments)
Thx
https://review.coreboot.org/c/coreboot/+/39821/16/src/northbridge/intel/i945... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/16/src/northbridge/intel/i945... PS16, Line 913: MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff;
Don't move this write
Done
https://review.coreboot.org/c/coreboot/+/39821/16/src/northbridge/intel/i945... PS16, Line 2149: if ((sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
Don't change this here please. It breaks verification...
Done
https://review.coreboot.org/c/coreboot/+/39821/16/src/northbridge/intel/i945... PS16, Line 2198: if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
Why did the CLOCKS_WIDTH macro disappear?
Done
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#19).
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
nb/i945: Split raminit into desktop and mobile version
Split up raminit.c to make maintenance easier.
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 83 insertions(+), 554 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/19
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 19:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/19/src/northbridge/intel/i945... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/19/src/northbridge/intel/i945... PS19, Line 407: printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32); line over 96 characters
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 19: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 19:
Uh, not sure why but it still differs... Does this still boot on the ECS 945G-M4?
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 19:
Patch Set 19:
Uh, not sure why but it still differs... Does this still boot on the ECS 945G-M4?
- it will boot only if : DIMM0 populated and all the other are not populated. - it will not boot but it will reach SeaBios if only DIMM1 is populated and all the other not populated.
in current patch , there is nothing done more than we already have in old raminit.c for 945GC.
would you test on the board you have ?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#20).
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
nb/i945: Split raminit into desktop and mobile version
Split up raminit.c to make maintenance easier.
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 96 insertions(+), 556 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/20
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 20:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/20/src/northbridge/intel/i945... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/20/src/northbridge/intel/i945... PS20, Line 407: printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32); line over 96 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 21:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/21/src/northbridge/intel/i945... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/21/src/northbridge/intel/i945... PS21, Line 407: printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32); line over 96 characters
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39821
to look at the new patch set (#22).
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
nb/i945: Split raminit into desktop and mobile version
Split up raminit.c to make maintenance easier.
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 83 insertions(+), 554 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/22
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Patch Set 22:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39821/22/src/northbridge/intel/i945... File src/northbridge/intel/i945/raminit_i945gc.c:
https://review.coreboot.org/c/coreboot/+/39821/22/src/northbridge/intel/i945... PS22, Line 396: printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32); line over 96 characters
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split raminit into desktop and mobile version ......................................................................
Abandoned
-
Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
-
HAOUAS Elyes (Code Review)
-
Paul Menzel (Code Review)