[S] Change in coreboot[main]: [RFC] nb/intel/haswell: Allow specifying SPD addresses in devicetree

[Angel Pons (Code Review)]

Attention is currently required from: Keith Hui.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79025?usp=email )

Change subject: [RFC] nb/intel/haswell: Allow specifying SPD addresses in devicetree
......................................................................

Patch Set 2:

(1 comment)

Patchset:

PS2: 
I'm not sure if the potential for confusion (SPD addresses can be specified in two different places, but only one of them is taken into account) outweighs the advantages of having a slightly simpler interface for some boards (those without SPD in CBFS).

When I came up with the Haswell SPD info approach, the main reason not to have SPD addresses in the devicetree was because it would spread information across files. The SPD-in-CBFS code uses the SPD addresses to discern between memory-down and empty slots; it makes sense to keep both things together, even if it means having a tiny bit of structure-filling code.