New patch to review for coreboot: 261113b asrock/e350m1/mainboard.c: GPP CLK

[Paul Menzel]

Paul Menzel ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5397

-gerrit

commit 261113bbe11c2776ae90a97bec52819f60e33aee
Author: Paul Menzel 
Date:   Sat Mar 22 23:22:29 2014 +0100

asrock/e350m1/mainboard.c: GPP CLK

According to Edward this might fix the problems with the Ethernet device
    not showing up sometimes.

Change-Id: Ibd839bb469f06cbbb8a50d6a0bc58ad967a1a5e1
    Signed-off-by: Paul Menzel 
---
 src/mainboard/asrock/e350m1/mainboard.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
index a98a179..e04bb92 100644
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ b/src/mainboard/asrock/e350m1/mainboard.c
@@ -54,6 +54,15 @@ static void mainboard_enable(device_t dev)
 {
    printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");

+	/* enable GPP CLK0 thru CLK3 (interleaved) */
+	/* disable GPP CLK4 thru SLT_GFX_CLK */
+	u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
+	*(misc_mem_clk_cntrl + 0) = 0xFF;
+	*(misc_mem_clk_cntrl + 1) = 0xFF;
+	*(misc_mem_clk_cntrl + 2) = 0x00;
+	*(misc_mem_clk_cntrl + 3) = 0x00;
+	*(misc_mem_clk_cntrl + 4) = 0x00;
+
    /*
     * Initialize ASF registers to an arbitrary address because someone
     * long ago set things up this way inside the SPD read code.  The