Change in coreboot[master]: soc/intel/skylake: Use ACPI timer config from soc common code
Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36930 )
Change subject: soc/intel/skylake: Use ACPI timer config from soc common code ......................................................................
soc/intel/skylake: Use ACPI timer config from soc common code
Replace the usage of structure member "PMTimerDisabled" of struct "soc_intel_skylake_config" in soc code with ACPI timer config defined under soc/intel/common/block/timer/Kconfig.
BUG=none TEST=none
Change-Id: I42fcf23525889d43f0291fcd662ca6b3597ab348 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/finalize.c 4 files changed, 2 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/36930/1
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 4711b1f..fa87946 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -54,7 +54,6 @@ register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1"
register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 1e0803c..3948f00 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -272,7 +272,7 @@ params->SataMode = config->SataMode; params->SataSpeedLimit = config->SataSpeedLimit; params->SataPwrOptEnable = config->SataPwrOptEnable; - params->EnableTcoTimer = !config->PmTimerDisabled; + params->EnableTcoTimer = CONFIG_ENABLE_ACPI_PM_TIMER;
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 63626663..39c42e5 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -498,7 +498,6 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ u8 HeciEnabled; - u8 PmTimerDisabled; /* Intel Speed Shift Technology */ u8 speed_shift_enable; /* diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 58a8701..1fb918e 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -90,7 +90,7 @@ * Disabling ACPI PM timer also switches off TCO */
- if (config->PmTimerDisabled) { + if (!CONFIG_ENABLE_ACPI_PM_TIMER) { reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); reg8 |= (1 << 1); write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36930 )
Change subject: soc/intel/skylake: Use ACPI timer config from soc common code ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36930/1/src/soc/intel/skylake/final... File src/soc/intel/skylake/finalize.c:
https://review.coreboot.org/c/coreboot/+/36930/1/src/soc/intel/skylake/final... PS1, Line 93: ENABLE_ACPI_PM_TIMER) CONFIG()
Meera Ravindranath has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36930 )
Change subject: soc/intel/skylake: Use ACPI timer config from soc common code ......................................................................
Abandoned
Merging this commit into 36064
-
Aaron Durbin (Code Review) -
Meera Ravindranath (Code Review)