[XS] Change in coreboot[main]: mb/google/brya/var/xol: Update NVMe clock source index to 0

[Eric Lai (Code Review)]

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80768?usp=email )

(

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/google/brya/var/xol: Update NVMe clock source index to 0
......................................................................

mb/google/brya/var/xol: Update NVMe clock source index to 0

Change ClkSrc index for NVME to 0 from 1 by referring to proto2
schematics.

BUG=b:326481458
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage

Change-Id: I7ea1cd7d8e16d4cee953e931d2f1829eae7d1978
Signed-off-by: Seunghwan Kim 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80768
Reviewed-by: Eric Lai 
Reviewed-by: Kapil Porwal 
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
---
M src/mainboard/google/brya/variants/xol/overridetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Eric Lai: Looks good to me, approved
  Subrata Banik: Looks good to me, approved
  Kapil Porwal: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb
index f840afe..0547dca 100644
--- a/src/mainboard/google/brya/variants/xol/overridetree.cb
+++ b/src/mainboard/google/brya/variants/xol/overridetree.cb
@@ -261,10 +261,10 @@
    		end
    	end
    	device ref pcie4_0 on
-		# Enable CPU PCIE RP 1 using CLK 1
+		# Enable CPU PCIE RP 1 using CLK 0
    		register "cpu_pcie_rp[CPU_RP(1)]" = "{
    			.clk_req = 1,
-				.clk_src = 1,
+				.clk_src = 0,
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
    		}"
    		probe STORAGE STORAGE_NVME