Change in coreboot[master]: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42462 )

Change subject: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init
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soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init

Since coreboot is initializing uart for debug logs, fsp should not reinitialize it.
Thus we need to set FSP UPD to skip Uart init in FSP and use settings done by coreboot

BUG=None
BRANCH=None
TEST=FSP is able to push debug logs on UART with this setting

Cq-Depend: TBD
Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07
Signed-off-by: Maulik V Vaghela 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42462
Tested-by: build bot (Jenkins) 
Reviewed-by: Ronak Kanabar 
---
M src/soc/intel/jasperlake/romstage/fsp_params.c
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Ronak Kanabar: Looks good to me, approved

diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index d9063b0..6d4055a 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -81,6 +81,7 @@
    m_cfg->VtdDisable = 0;

m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+	m_cfg->SerialIoUartDebugMode = config->SerialIoUartMode[CONFIG_UART_FOR_CONSOLE];

/* Display */
    m_cfg->DdiPortAConfig = config->DdiPortAConfig;