Lijian Zhao (lijian.zhao@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13371
-gerrit
commit 06c375f680d83d3280a1aaad7909c03c3bfa7a71 Author: Zhao, Lijian lijian.zhao@intel.com Date: Wed Dec 2 15:34:45 2015 -0800
soc/intel/apollolake: Fill northbridge ASL
Northbeidge resource assignment: Dynamic update memory resources for northbridge devices,exclude any fixed MMIO resources. Interrupt: ACPI aware OF will need _PRT table to get desired interrupt resource assigned and make device driver working. The logical device within SOC got fixed interrupt line.
Change-Id: I9595f9a12434fa423862836d19f7266d6023fc5a Signed-off-by: Zhao, Lijian lijian.zhao@intel.com --- src/soc/intel/apollolake/acpi/northbridge.asl | 129 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/pci_irqs.asl | 51 ++++++++++ 2 files changed, 180 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl new file mode 100644 index 0000000..7914604 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + + Name(_HID, EISAID("PNP0A08")) /* PCIe */ + Name(_CID, EISAID("PNP0A03")) /* PCI */ + Name(_ADR, 0) + Name(_BBN, 0) + +Device (MCHC) +{ + Name (_ADR, 0x00000000) /*Dev0 Func0 */ + + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset(0x60), + MCNF, 32, /* PCI MMCONF base */ + Offset (0xA8), /* Top of Upper Used Memory */ + TUUD, 64, + Offset(0xB4), + BGSM, 32, /* Base of Graphics Stolen Memory */ + Offset(0xBC), + TLUD, 32, /* Top of Low Useable DRAM */ + } +} + +/* Current Resource Settings */ +Method (_CRS, 0, Serialized) +{ + Name (MCRS, ResourceTemplate() + { + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,,) + + /* Data and GFX stolen memory */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000, + 0x04200000,,, STOM) + + /* + * PCI MMIO Region (TOLUD - PCI extended base MMCONF) + * This assumes that MMCONF is placed after PCI config space, + * and that no resources are allocated after the MMCONF region. + * This works, sicne MMCONF is hardcoded to 0xe00000000. + */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) + + /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) +}) + + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, PM01._MIN, PMIN) + CreateDwordField (MCRS, PM01._MAX, PMAX) + CreateDwordField (MCRS, PM01._LEN, PLEN) + + /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ + And(^MCHC.TLUD, 0xFFF00000, PMIN) + /* Read MMCONF base */ + And(^MCHC.MCNF, 0xF0000000, PMAX) + + /* Calculate PCI MMIO Length */ + Add(Subtract(PMAX, PMIN), 1, PLEN) + + /* Find GFX resource area in GCRS */ + CreateDwordField(MCRS, STOM._MIN, GMIN) + CreateDwordField(MCRS, STOM._MAX, GMAX) + CreateDwordField(MCRS, STOM._LEN, GLEN) + + /* Read BGSM */ + And(^MCHC.BGSM, 0xFFF00000, GMIN) + + /* Read TOLUD */ + And(^MCHC.TLUD, 0xFFF00000, GMAX) + Decrement(GMAX) + Add(Subtract(GMAX, GMIN), 1, GLEN) + + /* Patch PM02 range based on Memory Size */ + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) + + Store (^MCHC.TUUD, Local0) + + If (LLessEqual (Local0, 0x1000000000)) { + Store (0, MMIN) + Store (0, MLEN) + } + Subtract (Add (MMIN, MLEN), 1, MMAX) + + Return (MCRS) +} + +/* PCI IRQ assignment */ +#include "pci_irqs.asl" diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl new file mode 100644 index 0000000..9a737e2 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +Method(_PRT) +{ + Return(Package() { + + Package(){0x0000FFFF, 0, 0, 16}, /* NPK */ + Package(){0x0000FFFF, 1, 0, 24}, /* DPTF */ + Package(){0x0002FFFF, 0, 0, 19}, /* GEN */ + Package(){0x0003FFFF, 0, 0, 21}, /* IUNIT */ + Package(){0x000DFFFF, 1, 0, 40}, /* PMC */ + Package(){0x000EFFFF, 0, 0, 25}, /* Audio */ + Package(){0x000FFFFF, 0, 0, 20}, /* CSE */ + Package(){0x0011FFFF, 0, 0, 26}, /* ISH */ + Package(){0x0012FFFF, 0, 0, 19}, /* SATA */ + Package(){0x0013FFFF, 0, 0, 22}, /* PCIe-A 0 */ + Package(){0x0014FFFF, 0, 0, 22}, /* PCIe-B 0 */ + Package(){0x0015FFFF, 0, 0, 17}, /* xHCI */ + Package(){0x0015FFFF, 1, 0, 13}, /* xDCI */ + Package(){0x0016FFFF, 0, 0, 27}, /* I2C0 */ + Package(){0x0016FFFF, 1, 0, 28}, /* I2C1 */ + Package(){0x0016FFFF, 2, 0, 29}, /* I2C2 */ + Package(){0x0016FFFF, 3, 0, 30}, /* I2C3 */ + Package(){0x0017FFFF, 0, 0, 31}, /* I2C4 */ + Package(){0x0017FFFF, 1, 0, 32}, /* I2C5 */ + Package(){0x0017FFFF, 2, 0, 33}, /* I2C6 */ + Package(){0x0017FFFF, 3, 0, 34}, /* I2C7 */ + Package(){0x0018FFFF, 0, 0, 4}, /* UART0 */ + Package(){0x0018FFFF, 1, 0, 5}, /* UART1 */ + Package(){0x0018FFFF, 2, 0, 6}, /* UART2 */ + Package(){0x0018FFFF, 3, 0, 7}, /* UART3 */ + Package(){0x0019FFFF, 0, 0, 35}, /* SPI0 */ + Package(){0x0019FFFF, 1, 0, 36}, /* SPI1 */ + Package(){0x0019FFFF, 2, 0, 37}, /* SPI2 */ + Package(){0x001BFFFF, 0, 0, 3}, /* SDCard */ + Package(){0x001CFFFF, 0, 0, 39}, /* eMMC */ + Package(){0x001EFFFF, 0, 0, 42}, /* SDIO */ + Package(){0x001FFFFF, 0, 0, 20}, /* LPC */ + } + ) +}
-
Lijian Zhao