Rizwan Qureshi (rizwan.qureshi@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16301
-gerrit
commit a779af6035ef798569b9091b4fe79c494ca09471 Author: Rizwan Qureshi rizwan.qureshi@intel.com Date: Tue Aug 23 13:38:19 2016 +0530
kunimitsu: Add initial FSP2.0 support
Add placeholders for functions required when skylake uses FSP2.0 driver, keeping the fsp1.1 flow intact.
Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- src/mainboard/intel/kunimitsu/Makefile.inc | 4 ++++ src/mainboard/intel/kunimitsu/ramstage.c | 2 +- src/mainboard/intel/kunimitsu/romstage_fsp20.c | 21 +++++++++++++++++++++ src/mainboard/intel/kunimitsu/spd/Makefile.inc | 2 +- 4 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index cafa12c..86be420 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -34,3 +34,7 @@ ramstage-y += pei_data.c ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) +romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs)) +endif diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c index 563c715..44fb9cd 100644 --- a/src/mainboard/intel/kunimitsu/ramstage.c +++ b/src/mainboard/intel/kunimitsu/ramstage.c @@ -16,7 +16,7 @@ #include <soc/ramstage.h> #include "gpio.h"
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +void mainboard_silicon_init_params(FSP_SIL_UPD *params) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c new file mode 100644 index 0000000..10bdd21 --- /dev/null +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> + +void mainboard_memory_init_params(struct FSPM_UPD *mupd) +{ + /* TODO: Read and copy SPD and fill up Rcomp and DQ param */ +} diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc index 62d6fd4..0a9cb0f 100644 --- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc @@ -14,7 +14,7 @@ ## GNU General Public License for more details. ##
-romstage-y += spd.c +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += spd.c
SPD_BIN = $(obj)/spd.bin
-
Rizwan Qureshi