Change in coreboot[master]: soc/intel/xeon_sp: Add function to clear PMCON status bits

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61652 )

Change subject: soc/intel/xeon_sp: Add function to clear PMCON status bits
......................................................................

soc/intel/xeon_sp: Add function to clear PMCON status bits

This patch adds function to `clear PMCON status bits` into SoC directory
to align with other IA coreboot implementation.

BUG=b:211954778
TEST=None.

Signed-off-by: Subrata Banik 
Change-Id: I22650f539a1646f93f2c6494cbf54b8ca785d6ad
---
M src/soc/intel/xeon_sp/include/soc/pm.h
M src/soc/intel/xeon_sp/include/soc/pmc.h
M src/soc/intel/xeon_sp/pmutil.c
3 files changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/61652/1

diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h
index b4d6df9..63b15cd 100644
--- a/src/soc/intel/xeon_sp/include/soc/pm.h
+++ b/src/soc/intel/xeon_sp/include/soc/pm.h
@@ -121,4 +121,7 @@

void pmc_lock_smi(void);

+/* Clear PMCON status bits */
+void pmc_clear_pmcon_sts(void);
+
 #endif
diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h
index 69299b6..d499863 100644
--- a/src/soc/intel/xeon_sp/include/soc/pmc.h
+++ b/src/soc/intel/xeon_sp/include/soc/pmc.h
@@ -22,6 +22,7 @@
 #define PWRMBASE		0x48
 #define GEN_PMCON_A		0xa0
 #define  DISB			(1 << 23)
+#define  MS4V			(1 << 18)
 #define  GBL_RST_STS		(1 << 16)
 #define  SMI_LOCK		(1 << 4)
 #define GEN_PMCON_B		0xa4
diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c
index c63285c..eeb4f8d 100644
--- a/src/soc/intel/xeon_sp/pmutil.c
+++ b/src/soc/intel/xeon_sp/pmutil.c
@@ -179,3 +179,17 @@
    	reg8 |= SLEEP_AFTER_POWER_FAIL;
    pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8);
 }
+
+void pmc_clear_pmcon_sts(void)
+{
+	uint32_t reg_val;
+	uint8_t *addr;
+	addr = pmc_mmio_regs();
+
+	reg_val = read32(addr + GEN_PMCON_A);
+	/* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
+	 * while retaining MS4V write-1-to-clear bit */
+	reg_val &= ~(MS4V);
+
+	write32((addr + GEN_PMCON_A), reg_val);
+}