Change in coreboot[master]: nb/intel/x4x/raminit: Remove very long delay

[Arthur Heymans (Code Review)]

Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/19514 )

Change subject: nb/intel/x4x/raminit: Remove very long delay
......................................................................

nb/intel/x4x/raminit: Remove very long delay

It is not really known why there is such a long delay, but it works
fine without it.

TESTED on ga-g41m-es2l.

Change-Id: Idff5b978bbf161f8520d8000848e7b11c98c3945
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/19514
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: build bot (Jenkins) 
Reviewed-by: Martin Roth 
---
M src/northbridge/intel/x4x/raminit_ddr2.c
1 file changed, 0 insertions(+), 2 deletions(-)

Approvals:
  Philippe Mathieu-Daudé: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified
  Martin Roth: Looks good to me, approved

diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index 35caaa6..2178e24 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -1923,8 +1923,6 @@
    		die("Error: DDR is faster than FSB, halt\n");
    }

-	mdelay(250);
-
    // Program clock crossing
    clkcross_ddr2(s);
    printk(BIOS_DEBUG, "Done clk crossing\n");