[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Hung-Te Lin, Jarried Lin, Jason-jh Lin, Yidi Lin.

Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86027?usp=email )

Change subject: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra
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Patch Set 3: Code-Review+1

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86027/comment/d1891ee6_4d3501f2?usp... :
PS3, Line 12: request
requests

https://review.coreboot.org/c/coreboot/+/86027/comment/8721964a_10587f46?usp... :
PS3, Line 14: Otherwise, GCE will hang when accessing DRAM.
Move the first few words to the previous line

File src/soc/mediatek/mt8196/mminfra.c:

https://review.coreboot.org/c/coreboot/+/86027/comment/557889e4_bfc8ac10?usp... :
PS3, Line 35: 0x1
Maybe just `1` for consistency?