[XS] Change in coreboot[main]: soc/mediatek/mt8196: Adjust thermal trip point parameters

[Jarried Lin (Code Review)]

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu, Zhaoqing Jiu.

Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, Zhaoqing Jiu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86552?usp=email

to look at the new patch set (#4).

The following approvals got outdated and were removed:
Code-Review+2 by Yu-Ping Wu, Code-Review-1 by Yidi Lin, Verified+1 by build bot (Jenkins)

Change subject: soc/mediatek/mt8196: Adjust thermal trip point parameters
......................................................................

soc/mediatek/mt8196: Adjust thermal trip point parameters

Adjust thermal trip point parameters so the thermal can trigger the
interrupt at the expected trip point.

BRANCH=rauru
BUG=b:389026545
TEST=Boot up and check temperature in coreboot log:
[INFO ]  [LVTS_MSR] ts0 msr_all=141d0, msr_temp=16848, temp=41086
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 0 ts_name 0 temp 41086 rg_temp 41073(42059)
[INFO ]  [LVTS_MSR] ts1 msr_all=141e3, msr_temp=16867, temp=41540
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 1 ts_name 1 temp 41540 rg_temp 41526(42523)
[INFO ]  [LVTS_MSR] ts2 msr_all=14199, msr_temp=16793, temp=39772[0m
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 2 ts_name 2 temp 39772 rg_temp 39760(40715)
[INFO ]  [LVTS_MSR] ts3 msr_all=141c2, msr_temp=16834, temp=40751
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 3 ts_name 3 temp 40751 rg_temp 40739(41717)
[INFO ]  [LVTS_MSR] ts4 msr_all=141d0, msr_temp=16848, temp=41086
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 0 ts_name 4 temp 41086 rg_temp 41073(42059)
[INFO ]  [LVTS_MSR] ts5 msr_all=141b3, msr_temp=16819, temp=40393
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 1 ts_name 5 temp 40393 rg_temp 40380(41350)
[INFO ]  [LVTS_MSR] ts6 msr_all=14194, msr_temp=16788, temp=39652
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 2 ts_name 6 temp 39652 rg_temp 39641(40593)
[INFO ]  [LVTS_MSR] ts7 msr_all=14186, msr_temp=16774, temp=39318
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 3 ts_name 7 temp 39318 rg_temp 39307(40251)

Signed-off-by: Zhaoqing Jiu 
Change-Id: Ia7361edd7f75b82fff4241ec94488ed1ef07346f
---
M src/soc/mediatek/mt8196/include/soc/thermal_internal.h
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/86552/4