Change in coreboot[master]: soc,southbridge/intel: Avoid preprocessor with HAVE_SMI_HANDLER
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34254 )
Change subject: soc,southbridge/intel: Avoid preprocessor with HAVE_SMI_HANDLER ......................................................................
soc,southbridge/intel: Avoid preprocessor with HAVE_SMI_HANDLER
Change-Id: Id375999adad71d95d4968398e90bc3c07f65ea83 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/drivers/intel/fsp1_1/raminit.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/skylake/cpu.c M src/southbridge/intel/lynxpoint/lpc.c 5 files changed, 18 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/34254/1
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index bcc8eca..e71c9a2 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -53,6 +53,8 @@ UPD_DATA_REGION *upd_ptr; int fsp_verification_failure = 0; EFI_PEI_HOB_POINTERS hob_ptr; + char *smm_base; + size_t smm_size;
/* * Find and copy the UPD region to the stack so the platform can modify @@ -145,14 +147,11 @@ }
/* Display SMM area */ -#if CONFIG(HAVE_SMI_HANDLER) - char *smm_base; - size_t smm_size; - - smm_region((void **)&smm_base, &smm_size); - printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); - printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); -#endif + if (CONFIG(HAVE_SMI_HANDLER)) { + smm_region((void **)&smm_base, &smm_size); + printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); + printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); + }
/* Migrate CAR data */ printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); @@ -237,8 +236,8 @@ (unsigned int)fsp_reserved_memory_area))) { fsp_verification_failure = 1; printk(BIOS_ERR, "ERROR - Reserving FSP memory area!\n"); -#if CONFIG(HAVE_SMI_HANDLER) - if (cbmem_root != NULL) { + + if (CONFIG(HAVE_SMI_HANDLER) && cbmem_root != NULL) { size_t delta_bytes = (unsigned int)smm_base - cbmem_root->PhysicalStart - cbmem_root->ResourceLength; @@ -248,7 +247,6 @@ die_with_post_code(POST_INVALID_VENDOR_BINARY, "Please verify the chipset reserved size\n"); } -#endif }
/* Verify the FSP 1.1 HOB interface */ diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 7679724..df1d857 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -428,13 +428,11 @@
static void pch_set_acpi_mode(void) { -#if CONFIG(HAVE_SMI_HANDLER) - if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); } -#endif /* CONFIG_HAVE_SMI_HANDLER */ }
static void lpc_init(struct device *dev) diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 6d8eaab..2ad78a0 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -141,12 +141,9 @@
struct postcar_frame pcf; uintptr_t top_of_ram; - -#if CONFIG(HAVE_SMI_HANDLER) void *smm_base; size_t smm_size; uintptr_t tseg_base; -#endif
console_init();
@@ -177,7 +174,6 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
-#if CONFIG(HAVE_SMI_HANDLER) /* * Cache the TSEG region at the top of ram. This region is * not restricted to SMM mode until SMM has been relocated. @@ -185,10 +181,11 @@ * when relocating the SMM handler as well as using the TSEG * region for other purposes. */ - smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; - postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); -#endif + if (CONFIG(HAVE_SMI_HANDLER)) { + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + }
run_postcar_phase(&pcf); } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index a63809b..df08959 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -487,9 +487,8 @@ smm_southbridge_enable(GBL_EN);
/* Lock down the SMRAM space. */ -#if CONFIG(HAVE_SMI_HANDLER) - smm_lock(); -#endif + if (CONFIG(HAVE_SMI_HANDLER)) + smm_lock();
mp_run_on_all_cpus(vmx_configure, NULL, 2 * USECS_PER_MSEC);
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4efb83e..84032ca 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -491,8 +491,7 @@
static void pch_set_acpi_mode(void) { -#if CONFIG(HAVE_SMI_HANDLER) - if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); @@ -503,7 +502,6 @@ printk(BIOS_DEBUG, "done.\n"); #endif } -#endif /* CONFIG_HAVE_SMI_HANDLER */ }
static void pch_disable_smm_only_flashing(struct device *dev)
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34254 )
Change subject: soc,southbridge/intel: Avoid preprocessor with HAVE_SMI_HANDLER ......................................................................
Patch Set 1: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34254 )
Change subject: soc,southbridge/intel: Avoid preprocessor with HAVE_SMI_HANDLER ......................................................................
soc,southbridge/intel: Avoid preprocessor with HAVE_SMI_HANDLER
Change-Id: Id375999adad71d95d4968398e90bc3c07f65ea83 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34254 Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/drivers/intel/fsp1_1/raminit.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/skylake/cpu.c M src/southbridge/intel/lynxpoint/lpc.c 5 files changed, 18 insertions(+), 28 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index bcc8eca..e71c9a2 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -53,6 +53,8 @@ UPD_DATA_REGION *upd_ptr; int fsp_verification_failure = 0; EFI_PEI_HOB_POINTERS hob_ptr; + char *smm_base; + size_t smm_size;
/* * Find and copy the UPD region to the stack so the platform can modify @@ -145,14 +147,11 @@ }
/* Display SMM area */ -#if CONFIG(HAVE_SMI_HANDLER) - char *smm_base; - size_t smm_size; - - smm_region((void **)&smm_base, &smm_size); - printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); - printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); -#endif + if (CONFIG(HAVE_SMI_HANDLER)) { + smm_region((void **)&smm_base, &smm_size); + printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); + printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); + }
/* Migrate CAR data */ printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); @@ -237,8 +236,8 @@ (unsigned int)fsp_reserved_memory_area))) { fsp_verification_failure = 1; printk(BIOS_ERR, "ERROR - Reserving FSP memory area!\n"); -#if CONFIG(HAVE_SMI_HANDLER) - if (cbmem_root != NULL) { + + if (CONFIG(HAVE_SMI_HANDLER) && cbmem_root != NULL) { size_t delta_bytes = (unsigned int)smm_base - cbmem_root->PhysicalStart - cbmem_root->ResourceLength; @@ -248,7 +247,6 @@ die_with_post_code(POST_INVALID_VENDOR_BINARY, "Please verify the chipset reserved size\n"); } -#endif }
/* Verify the FSP 1.1 HOB interface */ diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 7679724..df1d857 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -428,13 +428,11 @@
static void pch_set_acpi_mode(void) { -#if CONFIG(HAVE_SMI_HANDLER) - if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); } -#endif /* CONFIG_HAVE_SMI_HANDLER */ }
static void lpc_init(struct device *dev) diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 6d8eaab..2ad78a0 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -141,12 +141,9 @@
struct postcar_frame pcf; uintptr_t top_of_ram; - -#if CONFIG(HAVE_SMI_HANDLER) void *smm_base; size_t smm_size; uintptr_t tseg_base; -#endif
console_init();
@@ -177,7 +174,6 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
-#if CONFIG(HAVE_SMI_HANDLER) /* * Cache the TSEG region at the top of ram. This region is * not restricted to SMM mode until SMM has been relocated. @@ -185,10 +181,11 @@ * when relocating the SMM handler as well as using the TSEG * region for other purposes. */ - smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; - postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); -#endif + if (CONFIG(HAVE_SMI_HANDLER)) { + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + }
run_postcar_phase(&pcf); } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index a63809b..df08959 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -487,9 +487,8 @@ smm_southbridge_enable(GBL_EN);
/* Lock down the SMRAM space. */ -#if CONFIG(HAVE_SMI_HANDLER) - smm_lock(); -#endif + if (CONFIG(HAVE_SMI_HANDLER)) + smm_lock();
mp_run_on_all_cpus(vmx_configure, NULL, 2 * USECS_PER_MSEC);
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4efb83e..84032ca 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -491,8 +491,7 @@
static void pch_set_acpi_mode(void) { -#if CONFIG(HAVE_SMI_HANDLER) - if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); @@ -503,7 +502,6 @@ printk(BIOS_DEBUG, "done.\n"); #endif } -#endif /* CONFIG_HAVE_SMI_HANDLER */ }
static void pch_disable_smm_only_flashing(struct device *dev)
-
Furquan Shaikh (Code Review) -
Kyösti Mälkki (Code Review)