Change in coreboot[master]: soc/amd/picasso: Make IVRS GNB entry depend on APIC enabled

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45116 )

Change subject: soc/amd/picasso: Make IVRS GNB entry depend on APIC enabled
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soc/amd/picasso: Make IVRS GNB entry depend on APIC enabled

Check whether FSP has enabled the GNB IOAPIC before generating
its entry in the IVRS table.

BUG=b:167421913, b:166519072
TEST=Verify no difference in IVRS before/after
BRANCH=Zork

Signed-off-by: Marshall Dawson 
Change-Id: I4caec158a252737cea5a1070fa4673faf3680b9f
---
M src/soc/amd/picasso/agesa_acpi.c
1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45116/1

diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c
index c76e943..6cdb04c 100644
--- a/src/soc/amd/picasso/agesa_acpi.c
+++ b/src/soc/amd/picasso/agesa_acpi.c
@@ -12,6 +12,8 @@
 #include <soc/pci_devs.h>
 #include <stdlib.h>
 #include <arch/mmio.h>
+#include <fsp/util.h>
+#include <FspGuids.h>

struct amd_fsp_acpi_hob_info {
    uint32_t table_size_in_bytes;
@@ -47,6 +49,9 @@

unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
 {
+	struct range_entry hob;
+	int status;
+
    ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current;
    memset(ivhd_ioapic, 0, sizeof(*ivhd_ioapic));

@@ -59,6 +64,14 @@
    ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC;
    current += sizeof(ivrs_ivhd_special_t);

+	/* FSP populates this generates this HOB if it initializes second IOAPIC */
+	status = fsp_find_range_hob(&hob, AMD_FSP_NB_IOAPIC_BASE_HOB_GUID.b);
+
+	if (status || !hob.begin) {
+		printk(BIOS_ERR, " NB_IOAPIC_BASE HOB was not found.\n");
+		return current;
+	}
+
    ivhd_ioapic = (ivrs_ivhd_special_t *)current;
    memset(ivhd_ioapic, 0, sizeof(*ivhd_ioapic));

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45116 )

Change subject: soc/amd/picasso: Make IVRS GNB entry depend on APIC enabled
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45116/1/src/soc/amd/picasso/agesa_a... 
File src/soc/amd/picasso/agesa_acpi.c:

https://review.coreboot.org/c/coreboot/+/45116/1/src/soc/amd/picasso/agesa_a... 
PS1, Line 67: populates this
remove this

[Marshall Dawson (Code Review)]

Marshall Dawson has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45116 )

Change subject: soc/amd/picasso: Make IVRS GNB entry depend on APIC enabled
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Abandoned

We'll always enable the GNB IOAPIC