Change in coreboot[master]: soc/intel/alderlake: Use PMC IPC to disable HECI1

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61458 )

Change subject: soc/intel/alderlake: Use PMC IPC to disable HECI1
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soc/intel/alderlake: Use PMC IPC to disable HECI1

This patch allows common CSE block to disable HECI1 device using PMC
IPC command `0xA9`.

Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for
Alder Lake to disable HECI1 device using PMC IPC.

Additionally, remove dead code that deals with HECI1 disabling using
in SMM as HECI1 disabling using PMC IPC is simpler solution.

Signed-off-by: Subrata Banik 
Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61458
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: EricR Lai 
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/finalize.c
M src/soc/intel/alderlake/smihandler.c
3 files changed, 3 insertions(+), 17 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  EricR Lai: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index fa95088..863150e 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -78,6 +78,7 @@
    select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
    select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N
    select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT
    select SOC_INTEL_COMMON_BLOCK_IPU
    select SOC_INTEL_COMMON_BLOCK_IRQ
    select SOC_INTEL_COMMON_BLOCK_MEMINIT
diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c
index 589ea59..880e1e0 100644
--- a/src/soc/intel/alderlake/finalize.c
+++ b/src/soc/intel/alderlake/finalize.c
@@ -106,6 +106,8 @@
    tbt_finalize();
    sa_finalize();
    heci_finalize();
+	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
+		heci1_disable();

/* Indicate finalize step with post code */
    post_code(POST_OS_BOOT);
diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c
index 61fecdf..e1fc5a0 100644
--- a/src/soc/intel/alderlake/smihandler.c
+++ b/src/soc/intel/alderlake/smihandler.c
@@ -1,28 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <device/pci_def.h>
-#include <intelblocks/cse.h>
 #include <intelblocks/smihandler.h>
 #include <soc/soc_chip.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>

-/*
- * Specific SOC SMI handler during ramstage finalize phase
- *
- * BIOS can't make CSME function disable as is due to POSTBOOT_SAI
- * restriction in place from ADP chipset. Hence create SMI Handler to
- * perform CSME function disabling logic during SMM mode.
- */
-void smihandler_soc_at_finalize(void)
-{
-	if (!CONFIG(HECI_DISABLE_USING_SMM))
-		return;
-
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
-		heci1_disable();
-}
-
 int smihandler_soc_disable_busmaster(pci_devfn_t dev)
 {
    /* Skip disabling PMC bus master to keep IO decode enabled */