[S] Change in coreboot[master]: mb/google/skyrim: Enable PCIe RTD3 support

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70740 )

Change subject: mb/google/skyrim: Enable PCIe RTD3 support
......................................................................

mb/google/skyrim: Enable PCIe RTD3 support

Add PCIe RTD3 support for Skyrim

BUG=b:245550573
TEST=Boot/Reboot cycles and Suspend_stress_test 10 times

Signed-off-by: JasonNien 
Change-Id: I7f01827613eea2f254bc42c7f5aebeeb969b163a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70740
Reviewed-by: Fred Reitberger 
Reviewed-by: Raul Rangel 
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
Reviewed-by: Eric Lai 
---
M src/mainboard/google/skyrim/Kconfig
M src/mainboard/google/skyrim/port_descriptors.c
M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
3 files changed, 31 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved
  Raul Rangel: Looks good to me, approved
  Fred Reitberger: Looks good to me, but someone else must approve
  Eric Lai: Looks good to me, approved

diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig
index a89cc82..53cdce2 100644
--- a/src/mainboard/google/skyrim/Kconfig
+++ b/src/mainboard/google/skyrim/Kconfig
@@ -23,6 +23,7 @@
    select DRIVERS_I2C_NAU8825
    select DRIVERS_USB_HUB
    select DRIVERS_UART_ACPI
+	select DRIVERS_PCIE_RTD3_DEVICE
    select DRIVERS_PCIE_GENERIC
    select EC_GOOGLE_CHROMEEC
    select EC_GOOGLE_CHROMEEC_ESPI
diff --git a/src/mainboard/google/skyrim/port_descriptors.c b/src/mainboard/google/skyrim/port_descriptors.c
index 3af2d85..d745bd7 100644
--- a/src/mainboard/google/skyrim/port_descriptors.c
+++ b/src/mainboard/google/skyrim/port_descriptors.c
@@ -28,7 +28,7 @@
    	.function_number = PCI_FUNC(SD_DEVFN),
    	.link_speed_capability = GEN3,
    	.turn_off_unused_lanes = true,
-		.link_aspm = ASPM_DISABLED,	// TODO: switch to ASPM_L1 after b:245550573
+		.link_aspm = ASPM_L1,
    	.link_hotplug = 3,
    	.gpio_group_id = GPIO_27,
    	.clk_req = CLK_REQ1,
@@ -42,7 +42,7 @@
    	.function_number = PCI_FUNC(NVME_DEVFN),
    	.link_speed_capability = GEN3,
    	.turn_off_unused_lanes = true,
-		.link_aspm = ASPM_DISABLED,	// TODO: switch to ASPM_L1 after b:245550573
+		.link_aspm = ASPM_L1,
    	.link_hotplug = 3,
    	.gpio_group_id = GPIO_6,
    	.clk_req = CLK_REQ0,
diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
index 3b98246..52019ab 100644
--- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
@@ -99,7 +99,13 @@
    	end
    	device ref iommu on end
    	device ref gpp_bridge_1 on end # SD
-		device ref gpp_bridge_2 on end # NVMe
+		device ref gpp_bridge_2 on
+			# Required so the NVMe gets placed into D3 when entering S0i3.
+			chip drivers/pcie/rtd3/device
+				register "name" = ""NVME""
+				device pci 00.0 on end
+			end
+		end # NVMe

device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
    		device ref gfx on end # Internal GPU (GFX)