Change in coreboot[master]: mb/intel/adlrvp: Configure TCSS, BT and WiFi related GPIOs

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50516 )

Change subject: mb/intel/adlrvp: Configure TCSS, BT and WiFi related GPIOs
......................................................................

mb/intel/adlrvp: Configure TCSS, BT and WiFi related GPIOs

This CL configures TCSS, BT and WiFi related GPIOs based on schematics.

BUG=None
TEST= BT, WIFI and TCSS functionalities validated with this change.

Signed-off-by: Francois Toguo 
Change-Id: Ie0e665275c281fcbad0d02ceb723cea433637711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50516
Reviewed-by: Maulik V Vaghela 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/adlrvp/gpio_m.c
1 file changed, 57 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Maulik V Vaghela: Looks good to me, approved

diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c
index 0cce828..6f89fd2 100644
--- a/src/mainboard/intel/adlrvp/gpio_m.c
+++ b/src/mainboard/intel/adlrvp/gpio_m.c
@@ -6,6 +6,63 @@

/* Pad configuration in ramstage */
 static const struct pad_config gpio_table[] = {
+	/* A12 : BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A12, 1, PLTRST),
+
+	/* H2 : WLAN_RST_N */
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
+	/* 8 : M.2_BTWIFI_SUS_CLK */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+	/* 9 : GPD_9_SLP_WLAN_N */
+	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+	/* 10 : GPD_10_SLP_S5_N */
+	PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+
+	/* D12 : WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_D12, 1, PLTRST),
+	/* D13 : WIFI_WAKE_N */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* D14 :  x1 PCIE slot1 PWREN / SML0B_CLK */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+	/* D15 : WWAN_DISABLE_N */
+	PAD_CFG_GPO(GPP_D15, 1, PLTRST),
+	/* D18 : WWAN WAKE N*/
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT),
+	/* H23 : CLKREQ5_WWAN_N */
+	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
+
+	/* F0 : CNV_BRI_DT_BT_UART2_RTS_N */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	/* F1 : CNV_BRI_RSP_BT_UART2_RXD */
+	PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
+	/* F2 : CNV_RGI_DT_BT_UART2_TXD */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	/* F3 : CNV_RGI_RSP_BT_UART2_CTS_N */
+	PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
+	/* F4 : CNV_RF_RESET_R_N */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	/* F5 : MODEM_CLKREQ_R */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
+	/* F6 : GPPC_F6_CNV_PA_BLANKING */
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+	/* H8 : CNV_MFUART2_RXD */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
+	/* H9 : CNV_MFUART2_TXD */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
+
+	/* A14 : TCPC01_TYPEA23_OC1_N */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	/* A15 :  USB_TYPEA_OC2_N */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* E18 : TBT_LSX0_TXD */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
+	/* E19 : TBT_LSX0_RXD */
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
+	/* E20 : TBT_LSX1_TXD */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
+	/* E21 : TBT_LSX1_RXD */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
+
    /* H4  : I2C0 SDA */
    PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
    /* H6  : I2C1 SDA */