Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48698 )
Change subject: arch/x86: Pass GNVS as parameter to SMM module ......................................................................
arch/x86: Pass GNVS as parameter to SMM module
Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/x86/smm/smm_module_handler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c 27 files changed, 4 insertions(+), 210 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/48698/1
diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 3ba5684..8532d59 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -134,8 +134,10 @@
/* Make sure to set the global runtime. It's OK to race as the value * will be the same across CPUs as well as multiple SMIs. */ - if (smm_runtime == NULL) + if (smm_runtime == NULL) { smm_runtime = runtime; + gnvs = (void *)(uintptr_t)smm_runtime->gnvs_ptr; + }
if (cpu >= CONFIG_MAX_CPUS) { console_init(); diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 1810821..6fedba7 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -18,8 +18,6 @@ #include <soc/pm.h> #include <soc/nvs.h>
-static int smm_initialized; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -282,7 +280,6 @@ static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -312,23 +309,6 @@ enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 967a710..2df6410 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -497,8 +497,6 @@
if (gnvs) { acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index fd5ffce..9577536 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -396,9 +396,6 @@ else gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN;
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - /* Add it to DSDT */ acpigen_write_scope("\"); acpigen_write_name_dword("NVSA", (u32) gnvs); diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 6e250d8..a4fdb01 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -18,8 +18,6 @@ #include <soc/gpio.h> #include <smmstore.h>
-static int smm_initialized; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -261,7 +259,6 @@ static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -291,23 +288,6 @@ enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 73b83e4..5a29b02 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -646,9 +646,6 @@ } }
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - /* Add it to DSDT. */ acpigen_write_scope("\"); acpigen_write_name_dword("NVSA", (u32) gnvs); diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index fd5d452..5ed52d8 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -23,8 +23,6 @@ #include <drivers/intel/gma/i915_reg.h> #include <smmstore.h>
-static u8 smm_initialized = 0; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -313,7 +311,6 @@ static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -333,24 +330,6 @@ enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index d2177294..69f7a59 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -232,8 +232,6 @@
if (gnvs) { acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index dc32970..51a3003 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -330,8 +330,6 @@ const struct smm_save_state_ops *save_state_ops) { uint8_t reg8; - void *state = NULL; - static int smm_initialized = 0;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -361,25 +359,6 @@ pmc_enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = find_save_state(save_state_ops, reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - uint32_t reg_ebx = save_state_ops->get_reg(state, RBX); - gnvs = (struct global_nvs *)(uintptr_t)reg_ebx; - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(save_state_ops); diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index e7d29ff..2a847ed 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -258,8 +258,6 @@
if (gnvs) { acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index cae8b9b..ae15795 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -17,8 +17,6 @@ #include <soc/pm.h> #include <soc/nvs.h>
-static int smm_initialized; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -221,7 +219,6 @@ static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -252,20 +249,6 @@ case APM_CNT_FINALIZE: finalize(); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) southbridge_smi_store(); diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 0083be5..d654a58 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -552,8 +552,6 @@
if (gnvs) { acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 4c17eea..184eb6b 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -216,8 +216,6 @@
if (gnvs) { acpi_create_gnvs(gnvs); - /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ - // apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 8af8065..4515261 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -659,8 +659,6 @@ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #endif
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 40672f8..1a9e5b4 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -185,23 +185,6 @@ xhci_sleep(slp_type); }
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - struct region r = {(uintptr_t)gnvs, sizeof(struct global_nvs)}; - if (smm_region_overlaps_handler(&r)) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index c175647..c9cf544 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -4,7 +4,6 @@ #define INTEL_COMMON_PMUTIL_H
#include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h>
#define D31F0_PMBASE 0x40 #define D31F0_GEN_PMCON_1 0xa0 @@ -129,10 +128,8 @@ void southbridge_smm_xhci_sleep(u8 slp_type); void gpi_route_interrupt(u8 gpi, u8 mode); void southbridge_gate_memory_reset(void); -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); void southbridge_finalize_all(void); void southbridge_smi_monitor(void); -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); void pch_log_state(void);
#endif /*INTEL_COMMON_PMUTIL_H */ diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7610aa1..d59e29c 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -17,8 +17,6 @@
#include "pmutil.h"
-static int smm_initialized = 0; - u16 get_pmbase(void) { return lpc_get_pmbase(); @@ -198,7 +196,7 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) +static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) { em64t101_smm_state_save_area_t *state; int node; @@ -302,14 +300,6 @@ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - southbridge_update_gnvs(reg8, &smm_initialized); - break; case APM_CNT_FINALIZE: if (mainboard_finalized) { printk(BIOS_DEBUG, "SMI#: Already finalized\n"); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9ac8942..4db9351 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -491,8 +491,6 @@
acpi_create_gnvs(gnvs);
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index f1be5c2..03480a7 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -19,11 +19,6 @@
/* While we read PMBASE dynamically in case it changed, let's initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; - -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { }
int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 652da54..821a0b7 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -461,8 +461,6 @@ memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs);
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 537e544..046cc2b 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -14,10 +14,6 @@ struct global_nvs *gnvs; #endif
-/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 1f4cf29..ad9bac1 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -485,8 +485,6 @@ memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs);
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 7d79620..6a6c5b4 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -13,11 +13,6 @@ * initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; - -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { }
int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index d2a3404..0895ddd 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -555,8 +555,6 @@ gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu();
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 0c5e954..e83a9de 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -147,22 +147,6 @@ #undef IOTRAP }
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)(uintptr_t)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 915c181..586e626 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -712,8 +712,6 @@ /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 9c68a54..bd44500 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -19,8 +19,6 @@ #include "pch.h" #include "nvs.h"
-static u8 smm_initialized = 0; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -262,7 +260,6 @@ static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; static int chipset_finalized = 0;
/* Emulate B2 register as the FADT / Linux expects it */ @@ -304,24 +301,6 @@ enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ROUTE_ALL_XHCI: usb_xhci_route_all(); break;
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48698 )
Change subject: arch/x86: Pass GNVS as parameter to SMM module ......................................................................
Patch Set 2: Code-Review+2
Hello build bot (Jenkins), Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48698
to look at the new patch set (#3).
Change subject: arch/x86: Pass GNVS as parameter to SMM module ......................................................................
arch/x86: Pass GNVS as parameter to SMM module
Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/x86/smm/smm_module_handler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/skylake/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c 26 files changed, 4 insertions(+), 208 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/48698/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48698 )
Change subject: arch/x86: Pass GNVS as parameter to SMM module ......................................................................
Patch Set 4: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48698 )
Change subject: arch/x86: Pass GNVS as parameter to SMM module ......................................................................
Patch Set 4: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/48698/4/src/cpu/x86/smm/smm_module_... File src/cpu/x86/smm/smm_module_handler.c:
https://review.coreboot.org/c/coreboot/+/48698/4/src/cpu/x86/smm/smm_module_... PS4, Line 139: gnvs = (void *)(uintptr_t)smm_runtime->gnvs_ptr; Hmmm, platforms had a call to `smm_points_to_smram` here, but I'm not sure if implementing this check here is easily doable... Thoughts?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48698 )
Change subject: arch/x86: Pass GNVS as parameter to SMM module ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48698/4/src/cpu/x86/smm/smm_module_... File src/cpu/x86/smm/smm_module_handler.c:
https://review.coreboot.org/c/coreboot/+/48698/4/src/cpu/x86/smm/smm_module_... PS4, Line 139: gnvs = (void *)(uintptr_t)smm_runtime->gnvs_ptr;
Hmmm, platforms had a call to `smm_points_to_smram` here, but I'm not sure if implementing this chec […]
The test was there to validate a user-supplied pointer in SMI handler. Given that coreboot was already supposed to raise APM_CNT_GNVS_UPDATE and set smm_initialized=1, can you determine if the test was ever actually reached (with user-supplied pointer).
This is no longer a user-supplied pointer and the SMI handler in question is removed.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48698 )
Change subject: arch/x86: Pass GNVS as parameter to SMM module ......................................................................
Patch Set 5: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/48698/4/src/cpu/x86/smm/smm_module_... File src/cpu/x86/smm/smm_module_handler.c:
https://review.coreboot.org/c/coreboot/+/48698/4/src/cpu/x86/smm/smm_module_... PS4, Line 139: gnvs = (void *)(uintptr_t)smm_runtime->gnvs_ptr;
The test was there to validate a user-supplied pointer in SMI handler. […]
Good point
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48698 )
Change subject: arch/x86: Pass GNVS as parameter to SMM module ......................................................................
arch/x86: Pass GNVS as parameter to SMM module
Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48698 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/x86/smm/smm_module_handler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/skylake/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c 26 files changed, 4 insertions(+), 208 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 3ba5684..8532d59 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -134,8 +134,10 @@
/* Make sure to set the global runtime. It's OK to race as the value * will be the same across CPUs as well as multiple SMIs. */ - if (smm_runtime == NULL) + if (smm_runtime == NULL) { smm_runtime = runtime; + gnvs = (void *)(uintptr_t)smm_runtime->gnvs_ptr; + }
if (cpu >= CONFIG_MAX_CPUS) { console_init(); diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 1810821..6fedba7 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -18,8 +18,6 @@ #include <soc/pm.h> #include <soc/nvs.h>
-static int smm_initialized; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -282,7 +280,6 @@ static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -312,23 +309,6 @@ enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 967a710..2df6410 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -497,8 +497,6 @@
if (gnvs) { acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index aa805fb..c9df526 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -397,9 +397,6 @@ else gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN;
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - /* Add it to DSDT */ acpigen_write_scope("\"); acpigen_write_name_dword("NVSA", (u32) gnvs); diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 6e250d8..a4fdb01 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -18,8 +18,6 @@ #include <soc/gpio.h> #include <smmstore.h>
-static int smm_initialized; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -261,7 +259,6 @@ static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -291,23 +288,6 @@ enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 73b83e4..5a29b02 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -646,9 +646,6 @@ } }
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - /* Add it to DSDT. */ acpigen_write_scope("\"); acpigen_write_name_dword("NVSA", (u32) gnvs); diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index fd5d452..5ed52d8 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -23,8 +23,6 @@ #include <drivers/intel/gma/i915_reg.h> #include <smmstore.h>
-static u8 smm_initialized = 0; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -313,7 +311,6 @@ static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -333,24 +330,6 @@ enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index e3e72fd..4a53c55 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -252,8 +252,6 @@
if (gnvs) { acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index dc32970..51a3003 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -330,8 +330,6 @@ const struct smm_save_state_ops *save_state_ops) { uint8_t reg8; - void *state = NULL; - static int smm_initialized = 0;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -361,25 +359,6 @@ pmc_enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = find_save_state(save_state_ops, reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - uint32_t reg_ebx = save_state_ops->get_reg(state, RBX); - gnvs = (struct global_nvs *)(uintptr_t)reg_ebx; - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(save_state_ops); diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 994b8b1..993338a 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -259,8 +259,6 @@
if (gnvs) { acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index cae8b9b..ae15795 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -17,8 +17,6 @@ #include <soc/pm.h> #include <soc/nvs.h>
-static int smm_initialized; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -221,7 +219,6 @@ static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -252,20 +249,6 @@ case APM_CNT_FINALIZE: finalize(); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) southbridge_smi_store(); diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index a7b5387..4272954 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -553,8 +553,6 @@
if (gnvs) { acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 8af8065..4515261 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -659,8 +659,6 @@ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #endif
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 40672f8..1a9e5b4 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -185,23 +185,6 @@ xhci_sleep(slp_type); }
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - struct region r = {(uintptr_t)gnvs, sizeof(struct global_nvs)}; - if (smm_region_overlaps_handler(&r)) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index c175647..c9cf544 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -4,7 +4,6 @@ #define INTEL_COMMON_PMUTIL_H
#include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h>
#define D31F0_PMBASE 0x40 #define D31F0_GEN_PMCON_1 0xa0 @@ -129,10 +128,8 @@ void southbridge_smm_xhci_sleep(u8 slp_type); void gpi_route_interrupt(u8 gpi, u8 mode); void southbridge_gate_memory_reset(void); -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); void southbridge_finalize_all(void); void southbridge_smi_monitor(void); -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); void pch_log_state(void);
#endif /*INTEL_COMMON_PMUTIL_H */ diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7610aa1..d59e29c 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -17,8 +17,6 @@
#include "pmutil.h"
-static int smm_initialized = 0; - u16 get_pmbase(void) { return lpc_get_pmbase(); @@ -198,7 +196,7 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) +static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) { em64t101_smm_state_save_area_t *state; int node; @@ -302,14 +300,6 @@ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - southbridge_update_gnvs(reg8, &smm_initialized); - break; case APM_CNT_FINALIZE: if (mainboard_finalized) { printk(BIOS_DEBUG, "SMI#: Already finalized\n"); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9ac8942..4db9351 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -491,8 +491,6 @@
acpi_create_gnvs(gnvs);
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index f1be5c2..03480a7 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -19,11 +19,6 @@
/* While we read PMBASE dynamically in case it changed, let's initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; - -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { }
int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 652da54..821a0b7 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -461,8 +461,6 @@ memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs);
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 537e544..046cc2b 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -14,10 +14,6 @@ struct global_nvs *gnvs; #endif
-/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 1f4cf29..ad9bac1 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -485,8 +485,6 @@ memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs);
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 7d79620..6a6c5b4 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -13,11 +13,6 @@ * initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; - -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { }
int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index d2a3404..0895ddd 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -555,8 +555,6 @@ gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu();
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 0c5e954..e83a9de 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -147,22 +147,6 @@ #undef IOTRAP }
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)(uintptr_t)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 915c181..586e626 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -712,8 +712,6 @@ /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
- /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 9c68a54..bd44500 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -19,8 +19,6 @@ #include "pch.h" #include "nvs.h"
-static u8 smm_initialized = 0; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -262,7 +260,6 @@ static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; static int chipset_finalized = 0;
/* Emulate B2 register as the FADT / Linux expects it */ @@ -304,24 +301,6 @@ enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ROUTE_ALL_XHCI: usb_xhci_route_all(); break;
-
Angel Pons (Code Review) -
Kyösti Mälkki (Code Review)
-
Patrick Georgi (Code Review)