Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Lance Zhao, Jason Glenesk, Matt Delco, Marshall Dawson, Tim Wawrzynczak, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57888 )
Change subject: soc/amd/cezanne,soc/intel/common: rework CPPC table generation ......................................................................
Patch Set 12:
(15 comments)
File src/cpu/intel/common/common_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825): https://review.coreboot.org/c/coreboot/+/57888/comment/f35fd8b9_0347af49 PS12, Line 108: config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825): https://review.coreboot.org/c/coreboot/+/57888/comment/39def05a_09a46c4b PS12, Line 110: config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825): https://review.coreboot.org/c/coreboot/+/57888/comment/d6854536_8027bee8 PS12, Line 111: config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825): https://review.coreboot.org/c/coreboot/+/57888/comment/1a503513_86f10c89 PS12, Line 112: config->regs[CPPC_GUARANTEED_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825): https://review.coreboot.org/c/coreboot/+/57888/comment/bd213a4b_5e3c57c4 PS12, Line 135: config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = ACPI_REG_MSR(IA32_HWP_REQUEST, 32, 10); line over 96 characters
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825): https://review.coreboot.org/c/coreboot/+/57888/comment/bec1ddde_10dfb3ca PS12, Line 18: config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825): https://review.coreboot.org/c/coreboot/+/57888/comment/f035eadb_fb18a92d PS12, Line 19: config->regs[CPPC_NOMINAL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825): https://review.coreboot.org/c/coreboot/+/57888/comment/8a7bb805_1ce645b3 PS12, Line 20: config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825): https://review.coreboot.org/c/coreboot/+/57888/comment/31ed55cc_055f4d3b PS12, Line 21: config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825): https://review.coreboot.org/c/coreboot/+/57888/comment/593c7e74_a1d87962 PS12, Line 23: config->regs[CPPC_DESIRED_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825): https://review.coreboot.org/c/coreboot/+/57888/comment/5b6293df_f8485d76 PS12, Line 24: config->regs[CPPC_MIN_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825): https://review.coreboot.org/c/coreboot/+/57888/comment/a309b9ad_6370cfad PS12, Line 25: config->regs[CPPC_MAX_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825): https://review.coreboot.org/c/coreboot/+/57888/comment/1240fa15_ad87787c PS12, Line 29: config->regs[CPPC_REF_PERF_COUNTER] = ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825): https://review.coreboot.org/c/coreboot/+/57888/comment/1127debd_0b5aa7ac PS12, Line 30: config->regs[CPPC_DELIVERED_PERF_COUNTER] = ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825): https://review.coreboot.org/c/coreboot/+/57888/comment/23c5ec9c_af8b5262 PS12, Line 39: config->regs[CPPC_PERF_PREF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8); line over 96 characters