Attention is currently required from: Federico Amedeo Izzo, Felix Singer.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email )
Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1)
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Patch Set 11:
(1 comment)
File src/mainboard/aoostar/wtr_r1/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/82010/comment/5b6038d3_ba12c976 :
PS10, Line 117: .clk_req = 2,
Tried this, but this time no SSD, no NICs, no WLAN.
Uh, that seems wrong... To make sure we're on the same page, you have to set this for each root port:
```register "pch_pcie_rp[PCH_RP(5)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER"```
And this for all clock sources (array indices):
```register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING"```
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