Change in coreboot[master]: soc/intel/*: Update microcode as specified for MP-init

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Nico Huber, Patrick Rudolph, Subrata Banik, Michael Niewöhner, Andrey Petrov, Nathaniel L Desimone.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49899 )

Change subject: soc/intel/*: Update microcode as specified for MP-init
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Patch Set 13:

(1 comment)

File src/soc/intel/alderlake/cpu.c:

https://review.coreboot.org/c/coreboot/+/49899/comment/98232514_233ec0dd 
PS13, Line 70: PRMRR
> > PRMRR isn't currently configured on those platforms, so a second microcode update isn't required a […]

Well, if we're not passing MicrocodeRegionBase to the FSP, then the 2nd reload won't be done by the FSP; ADL is the only platform that currently does it; I think Michael is right, it seems like the 2nd reload is mostly for setting PRMRRs, which are used by SGX & C6DRAM, so if those options are selected, I think the 2nd reload is required.