HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39027 )
Change subject: soc/mediatek: Fix typos in comments ......................................................................
soc/mediatek: Fix typos in comments
Also add missing whitespace.
Change-Id: I3361122d5232072e68d018e84219a262acf34001 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/mediatek/common/include/soc/pmic_wrap_common.h M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/emi.c M src/soc/mediatek/mt8173/include/soc/pmic_wrap.h M src/soc/mediatek/mt8173/mt6391.c M src/soc/mediatek/mt8183/spm.c 7 files changed, 11 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39027/1
diff --git a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h index 0b9f2d3..bf64164 100644 --- a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h +++ b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h @@ -69,7 +69,7 @@ return pwrap_wacs2(1, addr, wdata, 0, 0); }
-/* dewrapper defaule value */ +/* dewrapper default value */ enum { DEFAULT_VALUE_READ_TEST = 0x5aa5, WRITE_TEST_VALUE = 0xa55a @@ -81,7 +81,7 @@ TIMEOUT_WAIT_IDLE_US = 255 };
-/* manual commnd */ +/* manual command */ enum { OP_WR = 0x1, OP_CSH = 0x0, diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 58dce72..4fafb04 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -450,7 +450,7 @@ mrs_write(channel, rank, sdram_params->mrs_set.mrs_63, 10); /* MR10 -> ZQ Init, tZQINIT>=1us */ mrs_write(channel, rank, sdram_params->mrs_set.mrs_10, 1); - /* MR3 driving stregth set to max */ + /* MR3 driving strength set to max */ mrs_write(channel, rank, sdram_params->mrs_set.mrs_3, 1); /* MR1 */ mrs_write(channel, rank, sdram_params->mrs_set.mrs_1, 1); diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 492238a..f6c866b 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -971,9 +971,9 @@ dqdqs_perbit_dly[i].best_last_dqsdly_pass = -2; }
- /* 1. delay DQ,find the pass widnow (left boundary) + /* 1. delay DQ,find the pass window (left boundary) * 2. delay DQS find the pass window (right boundary) - * 3. find the best DQ / DQS to satify the middle value + * 3. find the best DQ / DQS to satisfy the middle value * of the overall pass window per bit * 4. set DQS delay to the max per byte, delay DQ to de-skew */ diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index f3ea761..d97b4d6 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -148,7 +148,7 @@ 9;
/* check if row address */ - /*00 is 13 bits, 01 is 14 bits, 10 is 15bits, 11 is 16 bits */ + /* 00 is 13 bits, 01 is 14 bits, 10 is 15bits, 11 is 16 bits */ bit_counter += ((value & ROW_ADDR_BITS_MASK) >> ROW_ADDR_BITS_SHIFT) + 13;
@@ -159,7 +159,7 @@ /* add bank address bit, LPDDR3 is 8 banks =2^3 */ bit_counter += 3;
- /*transfor bits to bytes */ + /* transfer bits to bytes */ return ((size_t)1 << (bit_counter - 3)); }
diff --git a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h index 3687a29..d6c58a5 100644 --- a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h +++ b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h @@ -125,7 +125,7 @@
check_member(mt8173_pwrap_regs, dcm_dbc_prd, 0x148);
-/* dewrapper regsister */ +/* dewrapper register */ enum { DEW_EVENT_OUT_EN = DEW_BASE + 0x0, DEW_DIO_EN = DEW_BASE + 0x2, diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index 2656d72..3f77c8a 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -201,7 +201,7 @@ pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x17, 0x7F, 0); /* [6:0]: VSRMCA15_VOSEL_SLEEP; Sleep mode setting on */ pwrap_write_field(PMIC_RG_VSRMCA15_CON11, 0x00, 0x7F, 0); - /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode referenc */ + /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode reference */ pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x1, 0x1, 8); /* [5:4]: VSRMCA15_VOSEL_TRANS_EN; rising & falling e */ pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x3, 0x3, 4); @@ -359,7 +359,7 @@ pwrap_write_field(PMIC_RG_VDRM_CON9, 0x43, 0x7F, 0); pwrap_write_field(PMIC_RG_VDRM_CON10, 0x43, 0x7F, 0);
- /* 26M clock amplitute adjust */ + /* 26M clock amplitude adjust */ pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x0, 0x3, 2); pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x1, 0x3, 11);
diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 024fe1c..020da93 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -274,7 +274,7 @@ offset += copy_size;
/* version */ - /* The termintating character should be contained in the spm binary */ + /* The terminating character should be contained in the spm binary */ assert(spm_bin[file_size - 1] == '\0'); assert(offset < file_size); printk(BIOS_DEBUG, "SPM: version = %s\n", spm_bin + offset);
Jacob Garber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39027 )
Change subject: soc/mediatek: Fix typos in comments ......................................................................
Patch Set 1: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39027 )
Change subject: soc/mediatek: Fix typos in comments ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39027/1/src/soc/mediatek/mt8173/emi... File src/soc/mediatek/mt8173/emi.c:
https://review.coreboot.org/c/coreboot/+/39027/1/src/soc/mediatek/mt8173/emi... PS1, Line 162: transfer I believe *transform* was meant originally.
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39027 )
Change subject: soc/mediatek: Fix typos in comments ......................................................................
Patch Set 1:
(1 comment)
Thank you
https://review.coreboot.org/c/coreboot/+/39027/1/src/soc/mediatek/mt8173/emi... File src/soc/mediatek/mt8173/emi.c:
https://review.coreboot.org/c/coreboot/+/39027/1/src/soc/mediatek/mt8173/emi... PS1, Line 162: transfer
I believe *transform* was meant originally.
so we divide by 8 ?
Hello Julius Werner, Jacob Garber, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39027
to look at the new patch set (#2).
Change subject: soc/mediatek: Fix typos in comments ......................................................................
soc/mediatek: Fix typos in comments
Also add missing whitespace.
Change-Id: I3361122d5232072e68d018e84219a262acf34001 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/mediatek/common/include/soc/pmic_wrap_common.h M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/emi.c M src/soc/mediatek/mt8173/include/soc/pmic_wrap.h M src/soc/mediatek/mt8173/mt6391.c M src/soc/mediatek/mt8183/spm.c 7 files changed, 11 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39027/2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39027 )
Change subject: soc/mediatek: Fix typos in comments ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39027/1/src/soc/mediatek/mt8173/emi... File src/soc/mediatek/mt8173/emi.c:
https://review.coreboot.org/c/coreboot/+/39027/1/src/soc/mediatek/mt8173/emi... PS1, Line 162: transfer
so we divide by 8 ?
kind of, it's: 2^(bit_counter-3) = 2^bit_counter / 2^3 = 2^bit_counter / 8
Hello Julius Werner, Jacob Garber, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39027
to look at the new patch set (#3).
Change subject: soc/mediatek: Fix typos in comments ......................................................................
soc/mediatek: Fix typos in comments
Also add missing whitespace.
Change-Id: I3361122d5232072e68d018e84219a262acf34001 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/mediatek/common/include/soc/pmic_wrap_common.h M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/emi.c M src/soc/mediatek/mt8173/include/soc/pmic_wrap.h M src/soc/mediatek/mt8173/mt6391.c M src/soc/mediatek/mt8183/spm.c 7 files changed, 11 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39027/3
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39027 )
Change subject: soc/mediatek: Fix typos in comments ......................................................................
Patch Set 3:
(1 comment)
Thx
https://review.coreboot.org/c/coreboot/+/39027/1/src/soc/mediatek/mt8173/emi... File src/soc/mediatek/mt8173/emi.c:
https://review.coreboot.org/c/coreboot/+/39027/1/src/soc/mediatek/mt8173/emi... PS1, Line 162: transfer
kind of, it's: 2^(bit_counter-3) = 2^bit_counter / 2^3 = 2^bit_counter / 8
Done
Jacob Garber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39027 )
Change subject: soc/mediatek: Fix typos in comments ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39027 )
Change subject: soc/mediatek: Fix typos in comments ......................................................................
soc/mediatek: Fix typos in comments
Also add missing whitespace.
Change-Id: I3361122d5232072e68d018e84219a262acf34001 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/39027 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Jacob Garber jgarber1@ualberta.ca --- M src/soc/mediatek/common/include/soc/pmic_wrap_common.h M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/emi.c M src/soc/mediatek/mt8173/include/soc/pmic_wrap.h M src/soc/mediatek/mt8173/mt6391.c M src/soc/mediatek/mt8183/spm.c 7 files changed, 11 insertions(+), 11 deletions(-)
Approvals: build bot (Jenkins): Verified Jacob Garber: Looks good to me, approved
diff --git a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h index 0b9f2d3..bf64164 100644 --- a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h +++ b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h @@ -69,7 +69,7 @@ return pwrap_wacs2(1, addr, wdata, 0, 0); }
-/* dewrapper defaule value */ +/* dewrapper default value */ enum { DEFAULT_VALUE_READ_TEST = 0x5aa5, WRITE_TEST_VALUE = 0xa55a @@ -81,7 +81,7 @@ TIMEOUT_WAIT_IDLE_US = 255 };
-/* manual commnd */ +/* manual command */ enum { OP_WR = 0x1, OP_CSH = 0x0, diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 58dce72..4fafb04 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -450,7 +450,7 @@ mrs_write(channel, rank, sdram_params->mrs_set.mrs_63, 10); /* MR10 -> ZQ Init, tZQINIT>=1us */ mrs_write(channel, rank, sdram_params->mrs_set.mrs_10, 1); - /* MR3 driving stregth set to max */ + /* MR3 driving strength set to max */ mrs_write(channel, rank, sdram_params->mrs_set.mrs_3, 1); /* MR1 */ mrs_write(channel, rank, sdram_params->mrs_set.mrs_1, 1); diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 492238a..f6c866b 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -971,9 +971,9 @@ dqdqs_perbit_dly[i].best_last_dqsdly_pass = -2; }
- /* 1. delay DQ,find the pass widnow (left boundary) + /* 1. delay DQ,find the pass window (left boundary) * 2. delay DQS find the pass window (right boundary) - * 3. find the best DQ / DQS to satify the middle value + * 3. find the best DQ / DQS to satisfy the middle value * of the overall pass window per bit * 4. set DQS delay to the max per byte, delay DQ to de-skew */ diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index f3ea761..12f0837 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -148,7 +148,7 @@ 9;
/* check if row address */ - /*00 is 13 bits, 01 is 14 bits, 10 is 15bits, 11 is 16 bits */ + /* 00 is 13 bits, 01 is 14 bits, 10 is 15bits, 11 is 16 bits */ bit_counter += ((value & ROW_ADDR_BITS_MASK) >> ROW_ADDR_BITS_SHIFT) + 13;
@@ -159,7 +159,7 @@ /* add bank address bit, LPDDR3 is 8 banks =2^3 */ bit_counter += 3;
- /*transfor bits to bytes */ + /* transform bits to bytes */ return ((size_t)1 << (bit_counter - 3)); }
diff --git a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h index 3687a29..d6c58a5 100644 --- a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h +++ b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h @@ -125,7 +125,7 @@
check_member(mt8173_pwrap_regs, dcm_dbc_prd, 0x148);
-/* dewrapper regsister */ +/* dewrapper register */ enum { DEW_EVENT_OUT_EN = DEW_BASE + 0x0, DEW_DIO_EN = DEW_BASE + 0x2, diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index 2656d72..3f77c8a 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -201,7 +201,7 @@ pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x17, 0x7F, 0); /* [6:0]: VSRMCA15_VOSEL_SLEEP; Sleep mode setting on */ pwrap_write_field(PMIC_RG_VSRMCA15_CON11, 0x00, 0x7F, 0); - /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode referenc */ + /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode reference */ pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x1, 0x1, 8); /* [5:4]: VSRMCA15_VOSEL_TRANS_EN; rising & falling e */ pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x3, 0x3, 4); @@ -359,7 +359,7 @@ pwrap_write_field(PMIC_RG_VDRM_CON9, 0x43, 0x7F, 0); pwrap_write_field(PMIC_RG_VDRM_CON10, 0x43, 0x7F, 0);
- /* 26M clock amplitute adjust */ + /* 26M clock amplitude adjust */ pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x0, 0x3, 2); pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x1, 0x3, 11);
diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 024fe1c..020da93 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -274,7 +274,7 @@ offset += copy_size;
/* version */ - /* The termintating character should be contained in the spm binary */ + /* The terminating character should be contained in the spm binary */ assert(spm_bin[file_size - 1] == '\0'); assert(offset < file_size); printk(BIOS_DEBUG, "SPM: version = %s\n", spm_bin + offset);
-
HAOUAS Elyes (Code Review) -
Jacob Garber (Code Review)
-
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)