Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51711 )
Change subject: soc/amd/cezanne: select HAVE_EM100_SUPPORT
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Patch Set 1:
(1 comment)
File src/soc/amd/cezanne/Kconfig:
https://review.coreboot.org/c/coreboot/+/51711/comment/37ea9746_d6384686
PS1, Line 25: HAVE_EM100_SUPPORT
currently it's at soc level and i'd say that the 16mhz in the common chipset code should be a safe f […]
Can we remove fch_spi_config_em100_modes? The PSP already sets up the SPI registers via EFS. This way if a board can support 33MHz with the EM100 it can be changed.
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