Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30899
Change subject: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON ......................................................................
AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON
I refused bolton under agesa/ once it turned out to be blobbed. We have AMD_PI_BOLTON.
Change-Id: Ic3cb9ada2d4f14b49f6ad54c58e6b950a1732b70 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/northbridge/amd/agesa/state_machine.h M src/southbridge/amd/agesa/Makefile.inc M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h M src/southbridge/amd/agesa/hudson/amd_pci_int_types.h M src/southbridge/amd/agesa/hudson/pci_devs.h M src/southbridge/amd/common/Makefile.inc 7 files changed, 9 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/30899/1
diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 81de242..43b205a 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -98,7 +98,6 @@ #define HAS_AGESA_FCH_OEM_CALLOUT \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc index fd13bcf..cf4d790 100644 --- a/src/southbridge/amd/agesa/Makefile.inc +++ b/src/southbridge/amd/agesa/Makefile.inc @@ -13,6 +13,5 @@ # GNU General Public License for more details. #
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index b80f734..3806ae7 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -13,16 +13,13 @@ ## GNU General Public License for more details. ##
-config SOUTHBRIDGE_AMD_AGESA_BOLTON - bool - config SOUTHBRIDGE_AMD_AGESA_HUDSON bool
config SOUTHBRIDGE_AMD_AGESA_YANGTZE bool
-if SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE +if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y @@ -71,21 +68,18 @@
config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" - default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON default "3rdparty/blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_XHCI_FWM
config HUDSON_IMC_FWM_FILE string "IMC firmware path and filename" - default "3rdparty/blobs/southbridge/amd/bolton/imc.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON default "3rdparty/blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_IMC_FWM
config HUDSON_GEC_FWM_FILE string "GEC firmware path and filename" - default "3rdparty/blobs/southbridge/amd/bolton/gec.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON default "3rdparty/blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_GEC_FWM @@ -180,7 +174,7 @@ bool default y
-endif # SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE +endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
if SOUTHBRIDGE_AMD_AGESA_YANGTZE config AZ_PIN diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h index 77d660c..148bccc 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -21,7 +21,7 @@ * into the FCH PCI_INTR 0xC00/0xC01 interrupt * routing table */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define FCH_INT_TABLE_SIZE 0x54 #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define FCH_INT_TABLE_SIZE 0x42 @@ -51,8 +51,8 @@ #define PIRQ_FC 0x14 /* FC */ #define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) -#define PIRQ_SD 0x17 /* SD */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#define PIRQ_SD 0x17 /* SD */ #endif #define PIRQ_IMC0 0x20 /* IMC INT0 */ #define PIRQ_IMC1 0x21 /* IMC INT1 */ @@ -70,9 +70,7 @@ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) -#define PIRQ_SD 0x42 /* SD 14h.7 */ -#endif -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#define PIRQ_SD 0x42 /* SD 14h.7 */ #define PIRQ_GPP0 0x50 /* GPP INT 0 */ #define PIRQ_GPP1 0x51 /* GPP INT 1 */ #define PIRQ_GPP2 0x52 /* GPP INT 2 */ diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h index 328818c..7d3ad07 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h @@ -16,7 +16,7 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) const char *intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h index 4706403..c6528ae 100644 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -26,13 +26,6 @@ #define XHCI_DEVID 0x7814 #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) -#define XHCI2_DEV 0x10 -#define XHCI2_FUNC 1 -#define XHCI2_DEVID 0x7814 -#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC) -#endif - /* SATA */ #define SATA_DEV 0x11 #define SATA_FUNC 0 @@ -75,7 +68,7 @@ #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
/* IDE */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define IDE_DEV 0x14 #define IDE_FUNC 1 # define IDE_DEVID 0x780C @@ -108,7 +101,7 @@ #define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC)
/* PCIe Ports */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define SB_PCIE_DEV 0x15 #define SB_PCIE_PORT1_FUNC 0 #define SB_PCIE_PORT2_FUNC 1 diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc index 92bb149..dcebdb5 100644 --- a/src/southbridge/amd/common/Makefile.inc +++ b/src/southbridge/amd/common/Makefile.inc @@ -1,6 +1,5 @@ ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30899
to look at the new patch set (#2).
Change subject: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON ......................................................................
AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON
I refused bolton under agesa/ once it turned out to be blobbed. We have AMD_PI_BOLTON.
Change-Id: Ic3cb9ada2d4f14b49f6ad54c58e6b950a1732b70 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/northbridge/amd/agesa/state_machine.h M src/southbridge/amd/agesa/Makefile.inc M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h M src/southbridge/amd/agesa/hudson/amd_pci_int_types.h M src/southbridge/amd/agesa/hudson/pci_devs.h M src/southbridge/amd/common/Makefile.inc M src/southbridge/amd/pi/hudson/Kconfig 8 files changed, 11 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/30899/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30899 )
Change subject: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON ......................................................................
Patch Set 2: Code-Review+1
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30899 )
Change subject: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/30899/2/src/southbridge/amd/pi/hudson/Kconfi... File src/southbridge/amd/pi/hudson/Kconfig:
PS2: Move into its own commit?
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30899 )
Change subject: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON ......................................................................
Patch Set 2: Code-Review+1
LGTM with the blobs addition separated out
Hello Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30899
to look at the new patch set (#3).
Change subject: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON ......................................................................
AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON
I refused bolton under agesa/ once it turned out to be blobbed. We have AMD_PI_BOLTON.
Change-Id: Ic3cb9ada2d4f14b49f6ad54c58e6b950a1732b70 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/northbridge/amd/agesa/state_machine.h M src/southbridge/amd/agesa/Makefile.inc M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h M src/southbridge/amd/agesa/hudson/amd_pci_int_types.h M src/southbridge/amd/agesa/hudson/pci_devs.h M src/southbridge/amd/common/Makefile.inc 7 files changed, 9 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/30899/3
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30899 )
Change subject: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON ......................................................................
Patch Set 3: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30899 )
Change subject: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON ......................................................................
Patch Set 3: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30899 )
Change subject: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON ......................................................................
AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON
I refused bolton under agesa/ once it turned out to be blobbed. We have AMD_PI_BOLTON.
Change-Id: Ic3cb9ada2d4f14b49f6ad54c58e6b950a1732b70 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/30899 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com Reviewed-by: Nico Huber nico.h@gmx.de --- M src/northbridge/amd/agesa/state_machine.h M src/southbridge/amd/agesa/Makefile.inc M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h M src/southbridge/amd/agesa/hudson/amd_pci_int_types.h M src/southbridge/amd/agesa/hudson/pci_devs.h M src/southbridge/amd/common/Makefile.inc 7 files changed, 9 insertions(+), 27 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 81de242..43b205a 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -98,7 +98,6 @@ #define HAS_AGESA_FCH_OEM_CALLOUT \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc index fd13bcf..cf4d790 100644 --- a/src/southbridge/amd/agesa/Makefile.inc +++ b/src/southbridge/amd/agesa/Makefile.inc @@ -13,6 +13,5 @@ # GNU General Public License for more details. #
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 22e0b6f..3bb9385 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -13,16 +13,13 @@ ## GNU General Public License for more details. ##
-config SOUTHBRIDGE_AMD_AGESA_BOLTON - bool - config SOUTHBRIDGE_AMD_AGESA_HUDSON bool
config SOUTHBRIDGE_AMD_AGESA_YANGTZE bool
-if SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE +if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y @@ -76,21 +73,18 @@
config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" - default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON default "3rdparty/blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_XHCI_FWM
config HUDSON_IMC_FWM_FILE string "IMC firmware path and filename" - default "3rdparty/blobs/southbridge/amd/bolton/imc.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON default "3rdparty/blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_IMC_FWM
config HUDSON_GEC_FWM_FILE string "GEC firmware path and filename" - default "3rdparty/blobs/southbridge/amd/bolton/gec.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON default "3rdparty/blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_GEC_FWM @@ -185,7 +179,7 @@ bool default y
-endif # SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE +endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
if SOUTHBRIDGE_AMD_AGESA_YANGTZE config AZ_PIN diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h index 77d660c..148bccc 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -21,7 +21,7 @@ * into the FCH PCI_INTR 0xC00/0xC01 interrupt * routing table */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define FCH_INT_TABLE_SIZE 0x54 #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define FCH_INT_TABLE_SIZE 0x42 @@ -51,8 +51,8 @@ #define PIRQ_FC 0x14 /* FC */ #define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) -#define PIRQ_SD 0x17 /* SD */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#define PIRQ_SD 0x17 /* SD */ #endif #define PIRQ_IMC0 0x20 /* IMC INT0 */ #define PIRQ_IMC1 0x21 /* IMC INT1 */ @@ -70,9 +70,7 @@ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) -#define PIRQ_SD 0x42 /* SD 14h.7 */ -#endif -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#define PIRQ_SD 0x42 /* SD 14h.7 */ #define PIRQ_GPP0 0x50 /* GPP INT 0 */ #define PIRQ_GPP1 0x51 /* GPP INT 1 */ #define PIRQ_GPP2 0x52 /* GPP INT 2 */ diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h index 328818c..7d3ad07 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h @@ -16,7 +16,7 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) const char *intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h index 4706403..c6528ae 100644 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -26,13 +26,6 @@ #define XHCI_DEVID 0x7814 #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) -#define XHCI2_DEV 0x10 -#define XHCI2_FUNC 1 -#define XHCI2_DEVID 0x7814 -#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC) -#endif - /* SATA */ #define SATA_DEV 0x11 #define SATA_FUNC 0 @@ -75,7 +68,7 @@ #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
/* IDE */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define IDE_DEV 0x14 #define IDE_FUNC 1 # define IDE_DEVID 0x780C @@ -108,7 +101,7 @@ #define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC)
/* PCIe Ports */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define SB_PCIE_DEV 0x15 #define SB_PCIE_PORT1_FUNC 0 #define SB_PCIE_PORT2_FUNC 1 diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc index 92bb149..dcebdb5 100644 --- a/src/southbridge/amd/common/Makefile.inc +++ b/src/southbridge/amd/common/Makefile.inc @@ -1,6 +1,5 @@ ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c
Balázs Vinarz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30899 )
Change subject: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON ......................................................................
Patch Set 4:
This commit just broke my port for a Bolton based motheboard, which I created in the weekend :) By the way the mobo was working with the SOUTHBRIDGE_AMD_AGESA_HUDSON config as well. Any ideas?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30899 )
Change subject: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON ......................................................................
Patch Set 4:
Patch Set 4:
This commit just broke my port for a Bolton based motheboard, which I created in the weekend :) By the way the mobo was working with the SOUTHBRIDGE_AMD_AGESA_HUDSON config as well. Any ideas?
The headers in AGESA being a mess, you cannot cross AGESA/binaryPI boundaries with a board port. If you have fam15tn or fam16kb with open-source AGESA, go with AGESA_HUDSON.
You can send me sudo lspci -xxxx output, maybe we can decide what hardware you really have. The part most likely not to work would be xhci / USB3.
Balázs Vinarz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30899 )
Change subject: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON ......................................................................
Patch Set 4:
Patch Set 4:
Patch Set 4:
This commit just broke my port for a Bolton based motheboard, which I created in the weekend :) By the way the mobo was working with the SOUTHBRIDGE_AMD_AGESA_HUDSON config as well. Any ideas?
The headers in AGESA being a mess, you cannot cross AGESA/binaryPI boundaries with a board port. If you have fam15tn or fam16kb with open-source AGESA, go with AGESA_HUDSON.
You can send me sudo lspci -xxxx output, maybe we can decide what hardware you really have. The part most likely not to work would be xhci / USB3.
I had a working XHCI once, but never again :) https://review.coreboot.org/c/coreboot/+/30987
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30899 )
Change subject: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON ......................................................................
Patch Set 4:
Bolton is more or less Hudson with an updated XHCI controller; as far as I remember the Hudson code was also valid for Bolton, but needed some Kconfig settings so that the right blob for the XHCI controller is used. So if I had seen the patch before it got merged, I'd at least -1ed it. This patch breaks XHCI for fam15tn/fam15rl devices that have a Bolton FCH
Balázs Vinarz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30899 )
Change subject: AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON ......................................................................
Patch Set 4:
Patch Set 4:
Bolton is more or less Hudson with an updated XHCI controller; as far as I remember the Hudson code was also valid for Bolton, but needed some Kconfig settings so that the right blob for the XHCI controller is used. So if I had seen the patch before it got merged, I'd at least -1ed it. This patch breaks XHCI for fam15tn/fam15rl devices that have a Bolton FCH
XHCI was non-working anyway (for me at least). I was just disappointed, because I had to work on the port again.
-
Balázs Vinarz (Code Review) -
Felix Held (Code Review)
-
Kyösti Mälkki (Code Review)
-
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)