Change in coreboot[master]: soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39110 )

Change subject: soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume
......................................................................

soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume

This patch makes all legacy 8254 FSP UPDs (Enable8254ClockGating and
Enable8254ClockGatingOnS3) depends on CONFIG_USE_LEGACY_8254_TIMER to
avoid discrepancy between S0 and S3 resume flow.

TEST=Able to boot to TianoCore in both S0 and S3 resume without
any hangs and errors.

Change-Id: Id6fe74a51537abbb9ff48db925e37a64e5b21f78
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/icelake/fsp_params.c
2 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39110/1

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index dc4a2a8..f1b8446 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -261,7 +261,7 @@

/* Legacy 8254 timer support */
    params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
-	params->Enable8254ClockGatingOnS3 = 1;
+	params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;

/* USB */
    for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c
index 7514be1..334fac8 100644
--- a/src/soc/intel/icelake/fsp_params.c
+++ b/src/soc/intel/icelake/fsp_params.c
@@ -140,7 +140,7 @@

/* Legacy 8254 timer support */
    params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
-	params->Enable8254ClockGatingOnS3 = 1;
+	params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;

/* S0ix */
    params->PchPmSlpS0Enable = config->s0ix_enable;

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39110 )

Change subject: soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume
......................................................................

Patch Set 1: Code-Review+2

Hmmmmm...

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39110 )

Change subject: soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39110/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39110/1//COMMIT_MSG@10 
PS1, Line 10: depends
depend

https://review.coreboot.org/c/coreboot/+/39110/1//COMMIT_MSG@14 
PS1, Line 14: any hangs and errors.
How can a payload be booted in S3 resume?

[Subrata Banik (Code Review)]

Hello Patrick Rudolph, Angel Pons, Duncan Laurie, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39110

to look at the new patch set (#2).

Change subject: soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume
......................................................................

soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume

This patch makes all legacy 8254 FSP UPDs (Enable8254ClockGating and
Enable8254ClockGatingOnS3) depend on CONFIG_USE_LEGACY_8254_TIMER to
avoid discrepancy between S0 and S3 resume flow.

TEST=Able to boot to TianoCore without any hangs and errors, also
verified S3 resume path doesn't clock gate 8254 timer using FSP-S UPD.

Change-Id: Id6fe74a51537abbb9ff48db925e37a64e5b21f78
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/icelake/fsp_params.c
2 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39110/2

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39110 )

Change subject: soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39110/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39110/1//COMMIT_MSG@10 
PS1, Line 10: depends
> depend

Ack

https://review.coreboot.org/c/coreboot/+/39110/1//COMMIT_MSG@14 
PS1, Line 14: any hangs and errors.
> How can a payload be booted in S3 resume?

Ack

[Duncan Laurie (Code Review)]

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39110 )

Change subject: soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume
......................................................................

Patch Set 2: Code-Review+2

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39110 )

Change subject: soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume
......................................................................

Patch Set 2: Code-Review+2

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39110 )

Change subject: soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume
......................................................................

soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume

This patch makes all legacy 8254 FSP UPDs (Enable8254ClockGating and
Enable8254ClockGatingOnS3) depend on CONFIG_USE_LEGACY_8254_TIMER to
avoid discrepancy between S0 and S3 resume flow.

TEST=Able to boot to TianoCore without any hangs and errors, also
verified S3 resume path doesn't clock gate 8254 timer using FSP-S UPD.

Change-Id: Id6fe74a51537abbb9ff48db925e37a64e5b21f78
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39110
Reviewed-by: Duncan Laurie 
Reviewed-by: Wonkyu Kim 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/icelake/fsp_params.c
2 files changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Duncan Laurie: Looks good to me, approved
  Angel Pons: Looks good to me, approved
  Wonkyu Kim: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index dc4a2a8..f1b8446 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -261,7 +261,7 @@

/* Legacy 8254 timer support */
    params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
-	params->Enable8254ClockGatingOnS3 = 1;
+	params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;

/* USB */
    for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c
index 7514be1..334fac8 100644
--- a/src/soc/intel/icelake/fsp_params.c
+++ b/src/soc/intel/icelake/fsp_params.c
@@ -140,7 +140,7 @@

/* Legacy 8254 timer support */
    params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
-	params->Enable8254ClockGatingOnS3 = 1;
+	params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;

/* S0ix */
    params->PchPmSlpS0Enable = config->s0ix_enable;

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39110 )

Change subject: soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume
......................................................................

Patch Set 3:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/879
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/878
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/877

Please note: This test is under development and might not be accurate at all!