Change in coreboot[master]: mb/intel/saddlebrook: Enable LPC IO Decode Range

[PraveenX Hodagatta Pranesh (Code Review)]

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/23620

Change subject: mb/intel/saddlebrook: Enable LPC IO Decode Range
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mb/intel/saddlebrook: Enable LPC IO Decode Range

SaddleBrook is Skylake based Platform which is Embedded with SIO.
LPC IO Decode range need to be enabled to Enable UART over SIO.

TEST: Build and Boot on SaddleBrook.

Change-Id: I4fce91ac47efb3060ba641d8e06438ac4e50dd24
Signed-off-by: praveen hodagatta pranesh 
---
M src/mainboard/intel/saddlebrook/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/23620/1

diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig
index df04286..a49804c 100644
--- a/src/mainboard/intel/saddlebrook/Kconfig
+++ b/src/mainboard/intel/saddlebrook/Kconfig
@@ -32,6 +32,7 @@
    select SUPERIO_NUVOTON_NCT6776_COM_A
    select SADDLEBROOK_USES_FSP1_1
    select HAVE_CMOS_DEFAULT
+	select SOC_IO_LPC_DECODE_ENABLE

config SADDLEBROOK_USES_FSP1_1