Change in coreboot[master]: soc/braswell/lpe: add resource allocation for BAR1

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/21103 )

Change subject: soc/braswell/lpe: add resource allocation for BAR1
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Patch Set 1:

(2 comments)

It would also be nice to know the state while the OS is running. No idea
how to be sure that you read from HW under Windows, but we can check
Linux at least. This should work:

# lspci -x -s 15.0

or maybe

# setpci 15.0 0x14.L
    # setpci 15.0 0x18.L

(assuming 15.0 is this dev)

https://review.coreboot.org/#/c/21103/1//COMMIT_MSG
Commit Message:

https://review.coreboot.org/#/c/21103/1//COMMIT_MSG@15
PS1, Line 15: TEST: boot google/cyan, observe MMIO values at BAR1 match
> I used RW Everything on Windows; it showed that the VID/SID, BAR0 address,

No idea about RW Everything. I want to be sure that the hardware
also knows about the configured MMIO range. Best option is to
dump the register late in coreboot.

https://review.coreboot.org/#/c/21103/1/src/soc/intel/braswell/lpe.c
File src/soc/intel/braswell/lpe.c:

https://review.coreboot.org/#/c/21103/1/src/soc/intel/braswell/lpe.c@162
PS1, Line 162: 		lpe_enable_acpi_mode(dev);
maybe dump BAR1/BAR2 here, e.g.

printk(BIOS_DEBUG, "lpe BAR1 0x%08x\n", pci_read_config32(dev, PCI_BASE_ADDRESS_1));
    printk(BIOS_DEBUG, "lpe BAR2 0x%08x\n", pci_read_config32(dev, PCI_BASE_ADDRESS_2));