[XS] Change in coreboot[main]: mb/starlabs/starlite_adl: Correct MODEM_CLKREQ configuration

[Sean Rhodes (Code Review)]

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86125?usp=email )

Change subject: mb/starlabs/starlite_adl: Correct MODEM_CLKREQ configuration
......................................................................

mb/starlabs/starlite_adl: Correct MODEM_CLKREQ configuration

This GPIO is used as MODEM_CLKREQ, which is Native Function 1.
Adjust the configuration accordingly.

Change-Id: Icc8be62e620a3e51826fb7c2c040da317e7eb470
Signed-off-by: Sean Rhodes 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86125
Reviewed-by: Matt DeVillier 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Matt DeVillier: Looks good to me, approved

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index cb4308f..14e57c5 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -296,8 +296,8 @@
    PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
    /* F4:		CNV RF Reset					*/
    PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
-	/* F5:		Not used		MODEM_CLKREQ		*/
-	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
+	/* F5:		MODEM_CLKREQ					*/
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
    /* F6:		CNV PA Blanking					*/
    PAD_NC(GPP_F6, NONE),
    /* F7:		TBT LSX VCCIO		Weak Internal PD 20K