[S] Change in coreboot[master]: soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL define

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73422 )

Change subject: soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL define
......................................................................

soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL define

Picasso and newer don't implement the P_CNT register to control the CPU
duty cycle and also trap the C state control IO addresses directly in
the CPU, so those won't reach the FCH. This register is unused in the
Picasso code and not even defined any more in the Cezanne PPR. The
Picasso PPR does define this register, but since it's useless and might
even just be a leftover form a pre-Zen CPU generation, drop the define.

Signed-off-by: Felix Held 
Change-Id: I3820db542c4714a100c7d36de673daa1a06e4a67
---
M src/soc/amd/picasso/include/soc/southbridge.h
1 file changed, 17 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/73422/1

diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index a3fb1a2..31f3ed6 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -47,7 +47,6 @@
 #define   TIMER_STS			BIT(0)
 #define PM1_CNT_BLK			0x62
 #define PM_TMR_BLK			0x64
-#define PM_CPU_CTRL			0x66
 #define PM_GPE0_BLK			0x68
 #define PM_ACPI_SMI_CMD			0x6a
 #define PM_ACPI_CONF			0x74