Patch set updated for coreboot: 5202df6 superio/ite/it8716f: Rewrite from hardcoded base addr
Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5565
-gerrit
commit 5202df6588f704bcd14a53d4588af87366204899 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Wed Apr 23 01:43:38 2014 +1000
superio/ite/it8716f: Rewrite from hardcoded base addr
Following the same reasoning as: HASHHERE superio/ite/it8721f: Rewrite from hardcoded base addr Removing hard coded magics and expose sio pnp api in romstage.
Change-Id: I27433cb1a84b3641a6110ecf6bd5021e00769aba Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/asus/m2n-e/romstage.c | 11 +++---- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 10 +++---- src/mainboard/gigabyte/m57sli/romstage.c | 9 ++++-- src/mainboard/via/pc2500e/romstage.c | 2 +- src/superio/ite/it8716f/Makefile.inc | 2 +- src/superio/ite/it8716f/chip.h | 3 +- src/superio/ite/it8716f/early_init.c | 37 ------------------------ src/superio/ite/it8716f/early_serial.c | 41 +++++++++++++++++++-------- src/superio/ite/it8716f/it8716f.h | 18 ++++++------ 9 files changed, 55 insertions(+), 78 deletions(-)
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 2f3baf6..6892b28 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -37,14 +37,14 @@ #include <spd.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/early_serial.c" -#include "superio/ite/it8716f/early_init.c" +#include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
static void memreset(int controllers, const struct mem_controller *ctrl) {} static inline void activate_spd_rom(const struct mem_controller *ctrl) {} @@ -104,11 +104,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- /* FIXME: This should be part of the Super I/O code/config. */ - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x23, 0x01); /* CLKIN = 24MHz */ - it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_24); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_mb_resource_map(); report_bist_failure(bist); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 4d215ae..86158c8 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -38,14 +38,14 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/early_serial.c" -#include "superio/ite/it8716f/early_init.c" +#include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/sis/sis966/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -125,10 +125,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x23, 0); - it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_mb_resource_map();
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 77eae09..4237b19 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -35,15 +35,14 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/early_serial.c" -#include "superio/ite/it8716f/early_init.c" +#include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO) +#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -118,6 +117,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+#if 0 pnp_enter_ext_func_mode(SERIAL_DEV); /* The following line will set CLKIN to 24 MHz, external */ pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11); @@ -132,6 +132,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); +#endif + it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_mb_resource_map();
diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 0728154..e374cf9 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -32,7 +32,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" -#include "superio/ite/it8716f/early_serial.c" +#include <superio/ite/it8716f/it8716f.h> #include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) diff --git a/src/superio/ite/it8716f/Makefile.inc b/src/superio/ite/it8716f/Makefile.inc index 5a67656..6b3c0ce 100644 --- a/src/superio/ite/it8716f/Makefile.inc +++ b/src/superio/ite/it8716f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
+romstage-$(CONFIG_SUPERIO_ITE_IT8716F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.c - diff --git a/src/superio/ite/it8716f/chip.h b/src/superio/ite/it8716f/chip.h index 33a265a..afdcd96 100644 --- a/src/superio/ite/it8716f/chip.h +++ b/src/superio/ite/it8716f/chip.h @@ -21,7 +21,6 @@ #ifndef SUPERIO_ITE_IT8716F_CHIP_H #define SUPERIO_ITE_IT8716F_CHIP_H
-#include <device/device.h> #include <pc80/keyboard.h>
struct superio_ite_it8716f_config { @@ -29,4 +28,4 @@ struct superio_ite_it8716f_config { struct pc_keyboard keyboard; };
-#endif +#endif /* SUPERIO_ITE_IT8716F_CHIP_H */ diff --git a/src/superio/ite/it8716f/early_init.c b/src/superio/ite/it8716f/early_init.c deleted file mode 100644 index cfac2a9..0000000 --- a/src/superio/ite/it8716f/early_init.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu yinghai.lu@amd.com for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include "it8716f.h" - -void it8716f_disable_dev(device_t dev) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); -} - -void it8716f_enable_dev(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/ite/it8716f/early_serial.c b/src/superio/ite/it8716f/early_serial.c index 02f0304..3103baf 100644 --- a/src/superio/ite/it8716f/early_serial.c +++ b/src/superio/ite/it8716f/early_serial.c @@ -2,9 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2006 Uwe Hermann uwe@hermann-uwe.de - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu yinghai.lu@amd.com for AMD. + * Copyright (C) 2007 AMD Written by Yinghai Lu yinghai.lu@amd.com for AMD. + * Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,13 +21,9 @@ */
#include <arch/io.h> +#include <device/pnp.h> #include "it8716f.h"
-/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - /* Global configuration registers. */ #define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ @@ -36,7 +31,7 @@ #define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
-static void pnp_enter_ext_func_mode(device_t dev) +static void it8716f_enter_conf(device_t dev) { u16 port = dev >> 8;
@@ -46,17 +41,39 @@ static void pnp_enter_ext_func_mode(device_t dev) outb((port == 0x4e) ? 0xaa : 0x55, port); }
-static void pnp_exit_ext_func_mode(device_t dev) +static void it8716f_exit_conf(device_t dev) { pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02); }
+static void it8716f_reg_write(device_t dev, u8 index, u8 value) +{ + it8716f_enter_conf(dev); + pnp_write_config(dev, index, value); + it8716f_exit_conf(dev); +} + + +/* + * in romstage.c + * #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) + * and pass: CLKIN_DEV + * IT8716F_UART_CLK_PREDIVIDE_24 + * IT8716F_UART_CLK_PREDIVIDE_48 (default) + */ +void it8716f_conf_clkin(device_t dev, u8 predivide) +{ + it8716f_reg_write(dev, IT8721F_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); +} + + +/* Enable the serial port(s). */ void it8716f_enable_serial(device_t dev, u16 iobase) { - pnp_enter_ext_func_mode(dev); + it8716f_enter_conf(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); + it8716f_exit_conf(dev); } diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h index 6657db4..12349ad 100644 --- a/src/superio/ite/it8716f/it8716f.h +++ b/src/superio/ite/it8716f/it8716f.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#ifndef SUPERIO_ITE_IT8716F_IT8716F_H -#define SUPERIO_ITE_IT8716F_IT8716F_H +#ifndef SUPERIO_ITE_IT8716F_H +#define SUPERIO_ITE_IT8716F_H
/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */
@@ -36,15 +36,15 @@ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */
+#define IT8716F_UART_CLK_PREDIVIDE_48 0x00 /* default */ +#define IT8716F_UART_CLK_PREDIVIDE_24 0x01 + +void it8716f_conf_clkin(device_t dev, u8 predivide); +void it8716f_enable_serial(device_t dev, u16 iobase); + #if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL /* Provided by mainboard, called by IT8716F superio.c. */ void init_ec(u16 base); #endif
-#if defined(__PRE_RAM__) -void it8716f_disable_dev(device_t dev); -void it8716f_enable_dev(device_t dev, u16 iobase); -void it8716f_enable_serial(device_t dev, u16 iobase); -#endif - -#endif +#endif /* SUPERIO_ITE_IT8716F_H */
-
Edward O'Callaghan