Change in coreboot[master]: mb/{adlrvp, brya, sm}: Set `pch_thermal_trip` for Dynamic Thermal Shu...

[Subrata Banik (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59270 )

Change subject: mb/{adlrvp, brya, sm}: Set `pch_thermal_trip` for Dynamic Thermal Shutdown
......................................................................

mb/{adlrvp, brya, sm}: Set `pch_thermal_trip` for Dynamic Thermal Shutdown

Set low maximum temp threshold value used for dynamic thermal sensor
shutdown consideration.

BUG=b:193774296

Change-Id: I7ee199c19a9d926a4135eeef3b3b481fbff74a79
Signed-off-by: Subrata Banik 
---
M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
5 files changed, 20 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/59270/1

diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
index 4ffc41d..e0d138e 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
@@ -72,6 +72,9 @@
         register "FivrSpreadSpectrum" = "FIVR_SS_1_5"

# Intel Common SoC Config
+	# NOTE: if any variant wants to override this value, use the same format
+	# as register "common_soc_config.pch_thermal_trip" = "value", instead of
+	# putting it under register "common_soc_config" in overridetree.cb file.
    #+-------------------+---------------------------+
    #| Field             |  Value                    |
    #+-------------------+---------------------------+
@@ -89,6 +92,7 @@
    		.early_init = 1,
    		.speed = I2C_SPEED_FAST,
    	},
+		.pch_thermal_trip = 100,
    }"

device domain 0 on
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index c89f24f..f877907 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -78,6 +78,9 @@
    register "FivrSpreadSpectrum" = "FIVR_SS_1_5"

# Intel Common SoC Config
+	# NOTE: if any variant wants to override this value, use the same format
+	# as register "common_soc_config.pch_thermal_trip" = "value", instead of
+	# putting it under register "common_soc_config" in overridetree.cb file.
    #+-------------------+---------------------------+
    #| Field             |  Value                    |
    #+-------------------+---------------------------+
@@ -122,6 +125,7 @@
    		.fall_time_ns = 400,
    		.data_hold_time_ns = 50,
    	},
+		.pch_thermal_trip = 100,
    }"

device domain 0 on
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index a00ad35..cc31f02 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -169,6 +169,9 @@
    register "CnviBtAudioOffload" = "true"

# Intel Common SoC Config
+	# NOTE: if any variant wants to override this value, use the same format
+	# as register "common_soc_config.pch_thermal_trip" = "value", instead of
+	# putting it under register "common_soc_config" in overridetree.cb file.
    register "common_soc_config" = "{
    	.i2c[0] = {
    		.speed = I2C_SPEED_FAST,
@@ -185,6 +188,7 @@
    	.i2c[5] = {
    		.speed = I2C_SPEED_FAST,
    	},
+		.pch_thermal_trip = 100,
    }"

# FIVR configurations
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index b73ded1..369b558 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -146,6 +146,9 @@
    register "PchHdaIDispCodecEnable" = "1"

# Intel Common SoC Config
+	# NOTE: if any variant wants to override this value, use the same format
+	# as register "common_soc_config.pch_thermal_trip" = "value", instead of
+	# putting it under register "common_soc_config" in overridetree.cb file.
    register "common_soc_config" = "{
    	.gspi[1] = {
    		.speed_mhz = 1,
@@ -166,6 +169,7 @@
    	.i2c[5] = {
    		.speed = I2C_SPEED_FAST,
    	},
+		.pch_thermal_trip = 100,
    }"

device domain 0 on
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index 6cf83d2..9307025 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -126,6 +126,9 @@
    }"

# Intel Common SoC Config
+	# NOTE: if any variant wants to override this value, use the same format
+	# as register "common_soc_config.pch_thermal_trip" = "value", instead of
+	# putting it under register "common_soc_config" in overridetree.cb file.
    #+-------------------+---------------------------+
    #| Field             |  Value                    |
    #+-------------------+---------------------------+
@@ -160,6 +163,7 @@
    	.i2c[5] = {
    		.speed = I2C_SPEED_FAST,
    	},
+		.pch_thermal_trip = 100,
    }"

device domain 0 on