[M] Change in coreboot[main]: mb/google/nissa/var/telith: Support x32 memory configuration

[Kun Liu (Code Review)]

Kun Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87212?usp=email )

Change subject: mb/google/nissa/var/telith: Support x32 memory configuration
......................................................................

mb/google/nissa/var/telith: Support x32 memory configuration

Use GPP_E19 level to determine whether x32 memory configuration is
supported.

BUG=b:405303038
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I969fea2aba858f76870c1a31ad4bd884ec9b6ff3
Signed-off-by: Kun Liu 
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/telith/Makefile.mk
M src/mainboard/google/brya/variants/telith/gpio.c
A src/mainboard/google/brya/variants/telith/memory.c
4 files changed, 133 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/87212/1

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 8886901..05c9a92 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -631,6 +631,7 @@
    select DRIVERS_INTEL_MIPI_CAMERA
    select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
    select SOC_INTEL_TWINLAKE
+	select ENFORCE_MEM_CHANNEL_DISABLE

config BOARD_GOOGLE_TEREID
    select BOARD_GOOGLE_BASEBOARD_NISSA
diff --git a/src/mainboard/google/brya/variants/telith/Makefile.mk b/src/mainboard/google/brya/variants/telith/Makefile.mk
index e7ef021..b67f308 100644
--- a/src/mainboard/google/brya/variants/telith/Makefile.mk
+++ b/src/mainboard/google/brya/variants/telith/Makefile.mk
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bootblock-y += gpio.c

+romstage-y += memory.c
 romstage-y += gpio.c

ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/telith/gpio.c b/src/mainboard/google/brya/variants/telith/gpio.c
index 0043111..75f7617 100644
--- a/src/mainboard/google/brya/variants/telith/gpio.c
+++ b/src/mainboard/google/brya/variants/telith/gpio.c
@@ -69,6 +69,9 @@
    /* R7 : DMIC_DATA_1A ==> NC */
    PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG),

+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG),
+
    /* Configure the virtual CNVi Bluetooth I2S GPIO pads */
    /* BT_I2S_BCLK */
    PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
@@ -112,6 +115,8 @@
    PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
    /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
    PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG),
 };

const struct pad_config *variant_gpio_override_table(size_t *num)
diff --git a/src/mainboard/google/brya/variants/telith/memory.c b/src/mainboard/google/brya/variants/telith/memory.c
new file mode 100644
index 0000000..7ac66b4
--- /dev/null
+++ b/src/mainboard/google/brya/variants/telith/memory.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg variant_memcfg = {
+	.type = MEM_TYPE_LP5X,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+	},
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = { 12,  9, 10, 11, 14, 13,  8, 15 },
+			.dq1 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+		},
+		.ddr1 = {
+			.dq0 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+			.dq1 = { 13,  9,  8, 11, 10, 14, 15, 12 },
+		},
+		.ddr2 = {
+			.dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
+			.dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
+		},
+		.ddr3 = {
+			.dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
+			.dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
+		},
+		.ddr4 = {
+			.dq0 = { 12,  9, 10, 11, 14, 13,  8, 15 },
+			.dq1 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+		},
+		.ddr5 = {
+			.dq0 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+			.dq1 = { 13,  9,  8, 11, 10, 14, 15, 12 },
+		},
+		.ddr6 = {
+			.dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
+			.dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
+		},
+		.ddr7 = {
+			.dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
+			.dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
+	},
+
+	.lp5x_config = {
+		.ccc_config = 0xff,
+	},
+
+	.ect = 1, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &variant_memcfg;
+}
+
+int variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * GPIO_MEM_CONFIG_0	GPP_E1
+	 * GPIO_MEM_CONFIG_1	GPP_E2
+	 * GPIO_MEM_CONFIG_2	GPP_E3
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_E1,
+		GPP_E2,
+		GPP_E3,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool variant_is_half_populated(void)
+{
+	/*
+	 * Ideally half_populated is used in platforms with multiple channels to
+	 * enable only one half of the channel. Alder Lake N has single channel,
+	 * and it would require for new structures to be defined in meminit block
+	 * driver for LPx memory configurations. In order to avoid adding new
+	 * structures, set half_populated to true. This has the same effect as
+	 * having single channel with 64-bit width.
+	*/
+	return true;
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}
+
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_E19 High -> One RAM Chip
+	 * GPP_E19 Low  -> Two RAM Chip
+	 */
+	if (gpio_get(GPP_E19)) {
+		/* Disable all other channels except first two on each controller */
+		return (BIT(2) | BIT(3));
+	}
+
+	return 0;
+}