Change in coreboot[master]: mainboard/google/hatch/puff: Toggle on TetonGlacierMode

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39041 )

Change subject: mainboard/google/hatch/puff: Toggle on TetonGlacierMode
......................................................................

mainboard/google/hatch/puff: Toggle on TetonGlacierMode

Leverage in Puff to avoid diskswap variants. Later this could become
part of the baseboard definition and hatch diskswap variants migrated
over to use it as well.

BUG=b:149171631
BRANCH=none
TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and
run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration
on Puff.

Change-Id: Ie87f0823f28457db397d495d9f1629d85cfd5215
Signed-off-by: Edward O'Callaghan 
---
M src/mainboard/google/hatch/variants/puff/overridetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/39041/1

diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index 4ffbfed..cca2d41 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -2,6 +2,9 @@
    # Enable heci communication
    register "HeciEnabled" = "1"

+	# Auto-switch between X4 NVMe and X2 NVMe.
+	register "TetonGlacierMode" = "1"
+
    register "SerialIoDevMode" = "{
    	[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
    	[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
@@ -166,6 +169,9 @@
    # PCIe port 7 for LAN
    register "PcieRpEnable[6]" = "1"
    register "PcieRpLtrEnable[6]" = "1"
+	# PCIe port 11 (x2) for NVMe hybrid storage devices
+	register "PcieRpEnable[10]" = "1"
+	register "PcieRpLtrEnable[10]" = "1"
    # Uses CLK SRC 0
    register "PcieClkSrcUsage[0]" = "6"
    register "PcieClkSrcClkReq[0]" = "0"
@@ -281,6 +287,7 @@
    		end
    	end # FSP requires func0 be enabled.
    	device pci 1c.6 on  end # RTL8111H Ethernet NIC (becomes RP1).
+		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
    	device pci 1e.3 off end # GSPI #1
    end

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39041 )

Change subject: mainboard/google/hatch/puff: Toggle on TetonGlacierMode
......................................................................

Patch Set 1: Code-Review+2

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39041 )

Change subject: mainboard/google/hatch/puff: Toggle on TetonGlacierMode
......................................................................

mainboard/google/hatch/puff: Toggle on TetonGlacierMode

Leverage in Puff to avoid diskswap variants. Later this could become
part of the baseboard definition and hatch diskswap variants migrated
over to use it as well.

BUG=b:149171631
BRANCH=none
TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and
run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration
on Puff.

Change-Id: Ie87f0823f28457db397d495d9f1629d85cfd5215
Signed-off-by: Edward O'Callaghan 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39041
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/mainboard/google/hatch/variants/puff/overridetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index 4ffbfed..cca2d41 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -2,6 +2,9 @@
    # Enable heci communication
    register "HeciEnabled" = "1"

+	# Auto-switch between X4 NVMe and X2 NVMe.
+	register "TetonGlacierMode" = "1"
+
    register "SerialIoDevMode" = "{
    	[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
    	[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
@@ -166,6 +169,9 @@
    # PCIe port 7 for LAN
    register "PcieRpEnable[6]" = "1"
    register "PcieRpLtrEnable[6]" = "1"
+	# PCIe port 11 (x2) for NVMe hybrid storage devices
+	register "PcieRpEnable[10]" = "1"
+	register "PcieRpLtrEnable[10]" = "1"
    # Uses CLK SRC 0
    register "PcieClkSrcUsage[0]" = "6"
    register "PcieClkSrcClkReq[0]" = "0"
@@ -281,6 +287,7 @@
    		end
    	end # FSP requires func0 be enabled.
    	device pci 1c.6 on  end # RTL8111H Ethernet NIC (becomes RP1).
+		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
    	device pci 1e.3 off end # GSPI #1
    end

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39041 )

Change subject: mainboard/google/hatch/puff: Toggle on TetonGlacierMode
......................................................................

Patch Set 2:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/932
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/931
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/930

Please note: This test is under development and might not be accurate at all!