Craig Hesling has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38623 )
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
hatch/mushu: Fix FPMCU pwr/rst gpio handling
This simply makes these variants consistent with other hatch variants.
This follows https://review.coreboot.org/c/coreboot/+/37459 .
BUG=b/148457345 TEST=None
Change-Id: I12dc0c3bead7672e2d3207771212efb0d246973a Signed-off-by: Craig Hesling hesling@chromium.org --- M src/mainboard/google/hatch/variants/hatch/Makefile.inc M src/mainboard/google/hatch/variants/hatch/gpio.c A src/mainboard/google/hatch/variants/hatch/ramstage.c M src/mainboard/google/hatch/variants/mushu/Makefile.inc M src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/ramstage.c 6 files changed, 70 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/38623/1
diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc index a990b5a..4bf640a 100644 --- a/src/mainboard/google/hatch/variants/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/variants/hatch/Makefile.inc @@ -19,5 +19,7 @@ SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101
-ramstage-y += gpio.c bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 862b28f..2c4fa50 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -55,8 +55,6 @@ * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ diff --git a/src/mainboard/google/hatch/variants/hatch/ramstage.c b/src/mainboard/google/hatch/variants/hatch/ramstage.c new file mode 100644 index 0000000..8e84308 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/hatch/variants/mushu/Makefile.inc index a990b5a..4bf640a 100644 --- a/src/mainboard/google/hatch/variants/mushu/Makefile.inc +++ b/src/mainboard/google/hatch/variants/mushu/Makefile.inc @@ -19,5 +19,7 @@ SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101
-ramstage-y += gpio.c bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index 09e1594..1453cab 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -57,8 +57,6 @@ * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ diff --git a/src/mainboard/google/hatch/variants/mushu/ramstage.c b/src/mainboard/google/hatch/variants/mushu/ramstage.c new file mode 100644 index 0000000..8e84308 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +}
Craig Hesling has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38623 )
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
Patch Set 1:
I aim to test on the hatch variant, but I do not have a way to directly test mushu.
The primary goal is to ensure that the RO image does not touch the FPMCU control lines.
Hello Bob Moragues, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38623
to look at the new patch set (#2).
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
hatch/mushu: Fix FPMCU pwr/rst gpio handling
This simply makes these variants consistent with other hatch variants and removes FPMCU control from the RO image.
This follows https://review.coreboot.org/c/coreboot/+/37459 .
BUG=b/148457345 TEST=None
Change-Id: I12dc0c3bead7672e2d3207771212efb0d246973a Signed-off-by: Craig Hesling hesling@chromium.org --- M src/mainboard/google/hatch/variants/hatch/Makefile.inc M src/mainboard/google/hatch/variants/hatch/gpio.c A src/mainboard/google/hatch/variants/hatch/ramstage.c M src/mainboard/google/hatch/variants/mushu/Makefile.inc M src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/ramstage.c 6 files changed, 70 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/38623/2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38623 )
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38623/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/hatch/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/38623/2/src/mainboard/google/hatch/... PS2, Line 25: ramstage-y += ramstage.c FYI these can go on one line
https://review.coreboot.org/c/coreboot/+/38623/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/hatch/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38623/2/src/mainboard/google/hatch/... PS2, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright 2020 Google LLC : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */ I believe coreboot is trying to (slowly) move over to SPDX headers, a la:
/* * This file is part of the coreboot project. * * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */
Hello Bob Moragues, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38623
to look at the new patch set (#3).
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
hatch/mushu: Fix FPMCU pwr/rst gpio handling
This simply makes these variants consistent with other hatch variants and removes FPMCU control from the RO image.
This follows https://review.coreboot.org/c/coreboot/+/37459 .
BUG=b/148457345 TEST=None
Change-Id: I12dc0c3bead7672e2d3207771212efb0d246973a Signed-off-by: Craig Hesling hesling@chromium.org --- M src/mainboard/google/hatch/variants/hatch/Makefile.inc M src/mainboard/google/hatch/variants/hatch/gpio.c A src/mainboard/google/hatch/variants/hatch/ramstage.c M src/mainboard/google/hatch/variants/mushu/Makefile.inc M src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/ramstage.c 6 files changed, 56 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/38623/3
Craig Hesling has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38623 )
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38623/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/hatch/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/38623/2/src/mainboard/google/hatch/... PS2, Line 25: ramstage-y += ramstage.c
FYI these can go on one line
Sure, but then future changes always incur a delete and add in git. Willing to change it if that is the way coreboot is going.
https://review.coreboot.org/c/coreboot/+/38623/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/hatch/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38623/2/src/mainboard/google/hatch/... PS2, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright 2020 Google LLC : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */
I believe coreboot is trying to (slowly) move over to SPDX headers, a la: […]
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38623 )
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
Patch Set 4: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/38623/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/hatch/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/38623/2/src/mainboard/google/hatch/... PS2, Line 25: ramstage-y += ramstage.c
Sure, but then future changes always incur a delete and add in git. […]
No big deal :) I don't think there's a consistent "style" there.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38623 )
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38623/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38623/4//COMMIT_MSG@10 PS4, Line 10: and removes FPMCU control from the RO image. Why?
https://review.coreboot.org/c/coreboot/+/38623/4//COMMIT_MSG@12 PS4, Line 12: https://review.coreboot.org/c/coreboot/+/37459 Please use commit hash or Change-Id and the summary when referencing other commits.
Hello Bob Moragues, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38623
to look at the new patch set (#5).
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
hatch/mushu: Fix FPMCU pwr/rst gpio handling
This simply makes these variants consistent with other hatch variants and removes FPMCU control from the RO image. Asserting reset in RO instead of in RW has no impact security or performance, but it does limit improvements to this process later.
This simply reinforces the concept brought in by fcd8c9e99e7f70e2b9494f2fa28a08ba13126daa .
BUG=b:148457345 TEST=None
Change-Id: I12dc0c3bead7672e2d3207771212efb0d246973a Signed-off-by: Craig Hesling hesling@chromium.org --- M src/mainboard/google/hatch/variants/hatch/Makefile.inc M src/mainboard/google/hatch/variants/hatch/gpio.c A src/mainboard/google/hatch/variants/hatch/ramstage.c M src/mainboard/google/hatch/variants/mushu/Makefile.inc M src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/ramstage.c 6 files changed, 56 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/38623/5
Hello Bob Moragues, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38623
to look at the new patch set (#6).
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
hatch/mushu: Fix FPMCU pwr/rst gpio handling
This simply makes these variants consistent with other hatch variants and removes FPMCU control from the RO image. Asserting reset in RO instead of in RW has no impact security or performance, but it does limit improvements to this process later.
This simply reinforces the concept brought in by commit fcd8c9e99e7f70e2b9494f2fa28a08ba13126daa .
BUG=b:148457345 TEST=None
Change-Id: I12dc0c3bead7672e2d3207771212efb0d246973a Signed-off-by: Craig Hesling hesling@chromium.org --- M src/mainboard/google/hatch/variants/hatch/Makefile.inc M src/mainboard/google/hatch/variants/hatch/gpio.c A src/mainboard/google/hatch/variants/hatch/ramstage.c M src/mainboard/google/hatch/variants/mushu/Makefile.inc M src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/ramstage.c 6 files changed, 56 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/38623/6
Craig Hesling has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38623 )
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
Patch Set 6:
(2 comments)
Thanks for the look Paul!
Please take another look.
https://review.coreboot.org/c/coreboot/+/38623/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38623/4//COMMIT_MSG@10 PS4, Line 10: and removes FPMCU control from the RO image.
Why?
Done
https://review.coreboot.org/c/coreboot/+/38623/4//COMMIT_MSG@12 PS4, Line 12: https://review.coreboot.org/c/coreboot/+/37459
Please use commit hash or Change-Id and the summary when referencing other commits.
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38623 )
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
Patch Set 6: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38623 )
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
Patch Set 6: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/38623/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38623/6//COMMIT_MSG@12 PS6, Line 12: performance, but it does limit improvements to this process later. Please reflow to use full text width of 75 characters.
https://review.coreboot.org/c/coreboot/+/38623/6//COMMIT_MSG@15 PS6, Line 15: fcd8c9e99e7f70e2b9494f2fa28a08ba13126daa Eight or ten characters followed by the summary.
fcd8c9e99e (hatch: Fix FPMCU pwr/rst gpio handling)
Hello Bob Moragues, Paul Menzel, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38623
to look at the new patch set (#7).
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
hatch/mushu: Fix FPMCU pwr/rst gpio handling
Asserting reset in RO instead of in RW has no impact on security or performance, but it does limit improvements to this process later. This fix removes reset line control from RO and makes these variants consistent with other hatch variants.
This fix reinforces the concept from commit fcd8c9e99e (hatch: Fix FPMCU pwr/rst gpio handling).
BUG=b:148457345 TEST=None
Change-Id: I12dc0c3bead7672e2d3207771212efb0d246973a Signed-off-by: Craig Hesling hesling@chromium.org --- M src/mainboard/google/hatch/variants/hatch/Makefile.inc M src/mainboard/google/hatch/variants/hatch/gpio.c A src/mainboard/google/hatch/variants/hatch/ramstage.c M src/mainboard/google/hatch/variants/mushu/Makefile.inc M src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/ramstage.c 6 files changed, 56 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/38623/7
Craig Hesling has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38623 )
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38623/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38623/6//COMMIT_MSG@12 PS6, Line 12: performance, but it does limit improvements to this process later.
Please reflow to use full text width of 75 characters.
Done
https://review.coreboot.org/c/coreboot/+/38623/6//COMMIT_MSG@15 PS6, Line 15: fcd8c9e99e7f70e2b9494f2fa28a08ba13126daa
Eight or ten characters followed by the summary. […]
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38623 )
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
hatch/mushu: Fix FPMCU pwr/rst gpio handling
Asserting reset in RO instead of in RW has no impact on security or performance, but it does limit improvements to this process later. This fix removes reset line control from RO and makes these variants consistent with other hatch variants.
This fix reinforces the concept from commit fcd8c9e99e (hatch: Fix FPMCU pwr/rst gpio handling).
BUG=b:148457345 TEST=None
Change-Id: I12dc0c3bead7672e2d3207771212efb0d246973a Signed-off-by: Craig Hesling hesling@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/38623 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/mainboard/google/hatch/variants/hatch/Makefile.inc M src/mainboard/google/hatch/variants/hatch/gpio.c A src/mainboard/google/hatch/variants/hatch/ramstage.c M src/mainboard/google/hatch/variants/mushu/Makefile.inc M src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/ramstage.c 6 files changed, 56 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc index a990b5a..4bf640a 100644 --- a/src/mainboard/google/hatch/variants/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/variants/hatch/Makefile.inc @@ -19,5 +19,7 @@ SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101
-ramstage-y += gpio.c bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 862b28f..2c4fa50 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -55,8 +55,6 @@ * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ diff --git a/src/mainboard/google/hatch/variants/hatch/ramstage.c b/src/mainboard/google/hatch/variants/hatch/ramstage.c new file mode 100644 index 0000000..5459f55 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/hatch/variants/mushu/Makefile.inc index a990b5a..4bf640a 100644 --- a/src/mainboard/google/hatch/variants/mushu/Makefile.inc +++ b/src/mainboard/google/hatch/variants/mushu/Makefile.inc @@ -19,5 +19,7 @@ SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101
-ramstage-y += gpio.c bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index a60662a..fd12eb0 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -59,8 +59,6 @@ * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ diff --git a/src/mainboard/google/hatch/variants/mushu/ramstage.c b/src/mainboard/google/hatch/variants/mushu/ramstage.c new file mode 100644 index 0000000..5459f55 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +}
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