Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35795 )
Change subject: sb/intel/i82801gx: Move CIR init to a common place ......................................................................
sb/intel/i82801gx: Move CIR init to a common place
Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/pineview/early_init.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/early_cir.c M src/southbridge/intel/i82801gx/i82801gx.h 22 files changed, 77 insertions(+), 324 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/35795/1
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 32a7871..89db57e 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -195,31 +195,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - /* next step only on ich7m b0 and later: */ - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 0228499..b3d1777 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -65,11 +65,7 @@ RCBA8(OIC) = 0x03; RCBA8(OIC);
- reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); }
static void ich7_enable_lpc(void) diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 632ef05..20a2b56 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -145,31 +145,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030509; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index dc589a5..dd48e59 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -142,10 +142,7 @@ RCBA8(0x31ff) = 0x03; RCBA8(0x31ff);
- reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); }
static void ich7_enable_lpc(void) diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index a22c90c..0bfbbfe 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -67,7 +67,8 @@ RCBA8(OIC);
RCBA32(FD) |= FD_INTLAN; - RCBA32(CG) = 0x00000001; + + ich7_setup_cir(); }
static void ich7_enable_lpc(void) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index a7c64bd..0b7aea4 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -204,31 +204,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index eaf05a2..65750cf 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -107,31 +107,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030509; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 989a0cb..d4ce940 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -96,16 +96,7 @@ RCBA8(OIC) = 0x03; RCBA8(OIC);
- RCBA32(GCS) = 0x00190464; - RCBA32(CG) = 0x00000000; - RCBA32(0x3430) = 0x00000001; - RCBA32(0x3e00) = 0xff000001; - RCBA32(0x3e08) = 0x00000080; - RCBA32(0x3e0c) = 0x00800000; - RCBA32(0x3e40) = 0xff000001; - RCBA32(0x3e48) = 0x00000080; - RCBA32(0x3e4c) = 0x00800000; - RCBA32(0x3f00) = 0x0000000b; + ich7_setup_cir(); }
static void ich7_enable_lpc(void) diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 82dbba5..1c3202f 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -169,31 +169,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index bad2b6d..f6fc8df 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -89,31 +89,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 74f8622..f27499b 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -55,10 +55,7 @@ RCBA8(0x31ff) = 0x03; RCBA8(0x31ff);
- reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); }
static void ich7_enable_lpc(void) diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index cee7c2a..2c2ad8b 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -213,31 +213,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - /* next step only on ich7m b0 and later: */ - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 9e83220..1fe16a9 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -129,31 +129,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index e4abab5..7329f0b 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -41,10 +41,7 @@ RCBA8(0x31ff) = 0x03; RCBA8(0x31ff);
- reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); }
static void ich7_enable_lpc(void) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 5a8ab94..8189f8a 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -129,31 +129,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 7f12091..09d5dae 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -129,31 +129,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 93b24a0..b1622ef 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -169,31 +169,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - /* next step only on ich7m b0 and later: */ - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
static void init_artec_dongle(void) diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index be6a5e2..1638f0e 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -135,26 +135,8 @@ pci_write_config8(LPC, 0x8, 0x1d); pci_write_config8(LPC, 0x8, 0x0); RCBA32(0x3410) = 0x00020465; - RCBA32(0x88) = 0x0011d000; - RCBA32(0x1fc) = 0x60f; - RCBA32(0x1f4) = 0x86000040; - RCBA32(0x214) = 0x10030509; - RCBA32(0x218) = 0x00020504; - RCBA32(0x220) = 0xc5; - RCBA32(0x3430) = 0x1; - RCBA32(0x2027) = 0x38f6a70d; - RCBA16(0x3e08) = 0x0080; - RCBA16(0x3e48) = 0x0080; - RCBA32(0x3e0e) = 0x00000080; - RCBA32(0x3e4e) = 0x00000080; - RCBA32(0x2034) = 0xb24577cc; - RCBA32(0x1c) = 0x03128010; - RCBA32(0x2010) = 0x400; - RCBA32(0x3400) = 0x4; - RCBA32(0x2080) = 0x18006007; - RCBA32(0x20a0) = 0x18006007; - RCBA32(0x20c0) = 0x18006007; - RCBA32(0x20e0) = 0x18006007; + + ich7_setup_cir();
pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1); pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1); diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 475def3..4156bf7e 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -62,7 +62,7 @@ int pch_silicon_supported(int type, int rev) { int cur_type = pch_silicon_type(); - int cur_rev = pch_silicon_revision(); + int cur_rev = pch_silicon_1revision();
switch (type) { case PCH_TYPE_CPT: diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 237c2d5..2e9d31a 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -35,5 +35,6 @@ smm-y += smihandler.c
romstage-y += early_smbus.c +romstage-y += early_cir.c
endif diff --git a/src/southbridge/intel/i82801gx/early_cir.c b/src/southbridge/intel/i82801gx/early_cir.c new file mode 100644 index 0000000..08f8019 --- /dev/null +++ b/src/southbridge/intel/i82801gx/early_cir.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include "i82801gx.h" + +/* Chipset Initialization Registers magic */ +void ich7_setup_cir(void) +{ + uint32_t reg32; + uint8_t revision = pci_read_config8(PCI_DEV(0, 31, 0), PCI_REVISION_ID); + uint16_t pci_id = pci_read_config16(PCI_DEV(0, 31, 0), PCI_DEVICE_ID); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(GCS); + reg32 |= (1 << 6); + RCBA32(GCS) = reg32; + RCBA32_AND_OR(0x3430, ~(3 << 0), 1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + /* Only on mobile variants of revision b0 or later */ + switch (pci_id) { + case 0x27b9: + case 0x27bc: + case 0x27bd: + if (revision > 2) { + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; + } + } +} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d615b40..8c85331 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -48,6 +48,7 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); +void ich7_setup_cir(void); #endif
#define MAINBOARD_POWER_OFF 0
Hello Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph, Angel Pons, build bot (Jenkins), Damien Zammit, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35795
to look at the new patch set (#2).
Change subject: sb/intel/i82801gx: Move CIR init to a common place ......................................................................
sb/intel/i82801gx: Move CIR init to a common place
Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/pineview/early_init.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/early_cir.c M src/southbridge/intel/i82801gx/i82801gx.h 21 files changed, 76 insertions(+), 327 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/35795/2
Hello Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph, Angel Pons, build bot (Jenkins), Damien Zammit, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35795
to look at the new patch set (#3).
Change subject: sb/intel/i82801gx: Move CIR init to a common place ......................................................................
sb/intel/i82801gx: Move CIR init to a common place
Some boards with the G41 chipset lacked programming CIR, so this change add that to those boards too.
Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/pineview/early_init.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/early_cir.c M src/southbridge/intel/i82801gx/i82801gx.h 21 files changed, 76 insertions(+), 327 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/35795/3
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35795 )
Change subject: sb/intel/i82801gx: Move CIR init to a common place ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35795/3/src/mainboard/asus/p5gc-mx/... File src/mainboard/asus/p5gc-mx/romstage.c:
https://review.coreboot.org/c/coreboot/+/35795/3/src/mainboard/asus/p5gc-mx/... PS3, Line 151: 0x10030509; this value is not the same
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35795 )
Change subject: sb/intel/i82801gx: Move CIR init to a common place ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35795/3/src/southbridge/intel/i8280... File src/southbridge/intel/i82801gx/early_cir.c:
https://review.coreboot.org/c/coreboot/+/35795/3/src/southbridge/intel/i8280... PS3, Line 28: 0x10030549 looks like this is RO what ever you enter here you will probably have 0x10030509
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35795 )
Change subject: sb/intel/i82801gx: Move CIR init to a common place ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35795/3/src/mainboard/asus/p5gc-mx/... File src/mainboard/asus/p5gc-mx/romstage.c:
https://review.coreboot.org/c/coreboot/+/35795/3/src/mainboard/asus/p5gc-mx/... PS3, Line 151: 0x10030509;
this value is not the same
Hmm in all the logs I have this value is indeed programmed programmed. Looking at serialICE logs on different targets 0x10030549 get programmed but 0x10030509 gets read back. I'll add a comment
Hello Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph, Angel Pons, build bot (Jenkins), Damien Zammit, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35795
to look at the new patch set (#4).
Change subject: sb/intel/i82801gx: Move CIR init to a common place ......................................................................
sb/intel/i82801gx: Move CIR init to a common place
Some boards with the G41 chipset lacked programming CIR, so this change add that to those boards too.
Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/pineview/early_init.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/early_cir.c M src/southbridge/intel/i82801gx/i82801gx.h 21 files changed, 77 insertions(+), 327 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/35795/4
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35795 )
Change subject: sb/intel/i82801gx: Move CIR init to a common place ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35795/3/src/mainboard/asus/p5gc-mx/... File src/mainboard/asus/p5gc-mx/romstage.c:
https://review.coreboot.org/c/coreboot/+/35795/3/src/mainboard/asus/p5gc-mx/... PS3, Line 151: 0x10030509;
this value is not the same […]
Ack
https://review.coreboot.org/c/coreboot/+/35795/3/src/southbridge/intel/i8280... File src/southbridge/intel/i82801gx/early_cir.c:
https://review.coreboot.org/c/coreboot/+/35795/3/src/southbridge/intel/i8280... PS3, Line 28: 0x10030549
looks like this is RO […]
Ack
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35795 )
Change subject: sb/intel/i82801gx: Move CIR init to a common place ......................................................................
Patch Set 4: Code-Review+2
Hello Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph, HAOUAS Elyes, Angel Pons, build bot (Jenkins), Damien Zammit, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35795
to look at the new patch set (#5).
Change subject: sb/intel/i82801gx: Move CIR init to a common place ......................................................................
sb/intel/i82801gx: Move CIR init to a common place
Some boards with the G41 chipset lacked programming CIR, so this change add that to those boards too.
Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/pineview/early_init.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/early_cir.c M src/southbridge/intel/i82801gx/i82801gx.h 20 files changed, 76 insertions(+), 302 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/35795/5
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35795 )
Change subject: sb/intel/i82801gx: Move CIR init to a common place ......................................................................
Patch Set 5:
Z61T was made a variant of T60, so manual rebase was needed.
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35795 )
Change subject: sb/intel/i82801gx: Move CIR init to a common place ......................................................................
Patch Set 5: Code-Review+2
Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35795 )
Change subject: sb/intel/i82801gx: Move CIR init to a common place ......................................................................
sb/intel/i82801gx: Move CIR init to a common place
Some boards with the G41 chipset lacked programming CIR, so this change add that to those boards too.
Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: HAOUAS Elyes ehaouas@noos.fr --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/pineview/early_init.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/early_cir.c M src/southbridge/intel/i82801gx/i82801gx.h 20 files changed, 76 insertions(+), 302 deletions(-)
Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 32a7871..89db57e 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -195,31 +195,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - /* next step only on ich7m b0 and later: */ - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 0228499..bb7a342 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -36,7 +36,6 @@
static void mb_lpc_setup(void) { - u32 reg32; /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); @@ -65,11 +64,7 @@ RCBA8(OIC) = 0x03; RCBA8(OIC);
- reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); }
static void ich7_enable_lpc(void) diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 632ef05..20a2b56 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -145,31 +145,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030509; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index dc589a5..30480ad 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -131,7 +131,6 @@
static void mb_lpc_setup(void) { - u32 reg32; /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); @@ -142,10 +141,7 @@ RCBA8(0x31ff) = 0x03; RCBA8(0x31ff);
- reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); }
static void ich7_enable_lpc(void) diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index a22c90c..0bfbbfe 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -67,7 +67,8 @@ RCBA8(OIC);
RCBA32(FD) |= FD_INTLAN; - RCBA32(CG) = 0x00000001; + + ich7_setup_cir(); }
static void ich7_enable_lpc(void) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index a7c64bd..0b7aea4 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -204,31 +204,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index eaf05a2..65750cf 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -107,31 +107,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030509; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 989a0cb..d4ce940 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -96,16 +96,7 @@ RCBA8(OIC) = 0x03; RCBA8(OIC);
- RCBA32(GCS) = 0x00190464; - RCBA32(CG) = 0x00000000; - RCBA32(0x3430) = 0x00000001; - RCBA32(0x3e00) = 0xff000001; - RCBA32(0x3e08) = 0x00000080; - RCBA32(0x3e0c) = 0x00800000; - RCBA32(0x3e40) = 0xff000001; - RCBA32(0x3e48) = 0x00000080; - RCBA32(0x3e4c) = 0x00800000; - RCBA32(0x3f00) = 0x0000000b; + ich7_setup_cir(); }
static void ich7_enable_lpc(void) diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 82dbba5..1c3202f 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -169,31 +169,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index bad2b6d..f6fc8df 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -89,31 +89,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 74f8622..81d5067 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -32,7 +32,6 @@
static void mb_lpc_setup(void) { - u32 reg32; /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); @@ -55,10 +54,7 @@ RCBA8(0x31ff) = 0x03; RCBA8(0x31ff);
- reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); }
static void ich7_enable_lpc(void) diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 7fa1b42..9995760 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -212,31 +212,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - /* next step only on ich7m b0 and later: */ - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 9e83220..1fe16a9 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -129,31 +129,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index e4abab5..cb84ce0 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -30,7 +30,6 @@
static void mb_lpc_setup(void) { - u32 reg32; /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); @@ -41,10 +40,7 @@ RCBA8(0x31ff) = 0x03; RCBA8(0x31ff);
- reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); }
static void ich7_enable_lpc(void) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 5a8ab94..8189f8a 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -129,31 +129,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
void mainboard_romstage_entry(void) diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index f550632..57d9c4a 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -168,31 +168,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - /* next step only on ich7m b0 and later: */ - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); }
static void init_artec_dongle(void) diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index be6a5e2..1638f0e 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -135,26 +135,8 @@ pci_write_config8(LPC, 0x8, 0x1d); pci_write_config8(LPC, 0x8, 0x0); RCBA32(0x3410) = 0x00020465; - RCBA32(0x88) = 0x0011d000; - RCBA32(0x1fc) = 0x60f; - RCBA32(0x1f4) = 0x86000040; - RCBA32(0x214) = 0x10030509; - RCBA32(0x218) = 0x00020504; - RCBA32(0x220) = 0xc5; - RCBA32(0x3430) = 0x1; - RCBA32(0x2027) = 0x38f6a70d; - RCBA16(0x3e08) = 0x0080; - RCBA16(0x3e48) = 0x0080; - RCBA32(0x3e0e) = 0x00000080; - RCBA32(0x3e4e) = 0x00000080; - RCBA32(0x2034) = 0xb24577cc; - RCBA32(0x1c) = 0x03128010; - RCBA32(0x2010) = 0x400; - RCBA32(0x3400) = 0x4; - RCBA32(0x2080) = 0x18006007; - RCBA32(0x20a0) = 0x18006007; - RCBA32(0x20c0) = 0x18006007; - RCBA32(0x20e0) = 0x18006007; + + ich7_setup_cir();
pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1); pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1); diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 237c2d5..2e9d31a 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -35,5 +35,6 @@ smm-y += smihandler.c
romstage-y += early_smbus.c +romstage-y += early_cir.c
endif diff --git a/src/southbridge/intel/i82801gx/early_cir.c b/src/southbridge/intel/i82801gx/early_cir.c new file mode 100644 index 0000000..4f08a43 --- /dev/null +++ b/src/southbridge/intel/i82801gx/early_cir.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include "i82801gx.h" + +/* Chipset Initialization Registers magic */ +void ich7_setup_cir(void) +{ + uint32_t reg32; + uint8_t revision = pci_read_config8(PCI_DEV(0, 31, 0), PCI_REVISION_ID); + uint16_t pci_id = pci_read_config16(PCI_DEV(0, 31, 0), PCI_DEVICE_ID); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + /* Although bit 6 is set, it is not read back */ + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(GCS); + reg32 |= (1 << 6); + RCBA32(GCS) = reg32; + RCBA32_AND_OR(0x3430, ~(3 << 0), 1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + /* Only on mobile variants of revision b0 or later */ + switch (pci_id) { + case 0x27b9: + case 0x27bc: + case 0x27bd: + if (revision >= 2) { + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; + } + } +} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d615b40..8c85331 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -48,6 +48,7 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); +void ich7_setup_cir(void); #endif
#define MAINBOARD_POWER_OFF 0
-
Arthur Heymans (Code Review) -
HAOUAS Elyes (Code Review)