Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33377 )
Change subject: soc/intel/common/block/xhci: Add API to disable USB devices ......................................................................
Patch Set 8:
(7 comments)
https://review.coreboot.org/c/coreboot/+/33377/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/mainboard.c:
https://review.coreboot.org/c/coreboot/+/33377/1/src/mainboard/google/octopu... PS1, Line 191: usb_device_disable
Prefer two improvements: […]
Done
https://review.coreboot.org/c/coreboot/+/33377/2/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/xhci.h:
https://review.coreboot.org/c/coreboot/+/33377/2/src/soc/intel/common/block/... PS2, Line 64: * the device tree.
It would be good to highlight that: […]
Done
https://review.coreboot.org/c/coreboot/+/33377/2/src/soc/intel/common/block/... PS2, Line 72: * in the device tree but are not used in certain situations like SKUs.
Again, it is important to highlight the difference here i.e. […]
Done
https://review.coreboot.org/c/coreboot/+/33377/2/src/soc/intel/common/block/... PS2, Line 74: port_id
How do you determine port type USB2 or USB3 from this?
Done. With the new callback mechanism the port type and port id are passed to mainboard to see if the port is enabled or not.
https://review.coreboot.org/c/coreboot/+/33377/2/src/soc/intel/common/block/... File src/soc/intel/common/block/xhci/xhci.c:
https://review.coreboot.org/c/coreboot/+/33377/2/src/soc/intel/common/block/... PS2, Line 98: port_id
I don't think it is correct to assume that port_id would apply to both USB2 and USB3 ports. […]
Ack
https://review.coreboot.org/c/coreboot/+/33377/3/src/soc/intel/common/block/... File src/soc/intel/common/block/xhci/xhci.c:
https://review.coreboot.org/c/coreboot/+/33377/3/src/soc/intel/common/block/... PS3, Line 79: Could not locate XHCI config in DT
XHCI device is what I meant as config. I have changed it to mean device.
Done
https://review.coreboot.org/c/coreboot/+/33377/3/src/soc/intel/common/block/... PS3, Line 86: config = port->chip_info; : if (!config) : continue;
Now that https://review.coreboot. […]
Done
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Karthik Ramasubramanian (Code Review)